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  KSZ8864RMN integrated 4-port 10/100 managed switch with two macs mii or rmii interfaces rev. 1.4 micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com september 2011 m9999-092011-1.4 general description the KSZ8864RMN is a highly-integrated, layer 2 managed 4-port switch with optimized design, plentiful features and smallest package size. it is designed for cost-sensitive 10/100mbps 4-port switch systems with on-chip termination, lowe st-power consumption, and small package to save system cost. it has 1.4gbps high- performance memory bandwidth, shared memory-based switch fabric with full non-blocking configuration. it also provides an extensive feature set such as the power management, programmable rate limiting and priority ratio, tag/port-based vlan, pac ket filtering, quality of service (qos), four queue prioritization, management interface, mib counters. port 3 and port 4 support either mii or rmii interfaces with sw3-mii/rmii and sw4- mii/rmii (see functional diagram) for KSZ8864RMN data interface. the KSZ8864RMN provides multiple cpu control/data interfaces to effectively address both current and emerging fast ethernet applications. the KSZ8864RMN consists of 10/100 fast ethernet phys with patented and enhanced mixed-signal technology, media access control (mac) units, a high- speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. the KSZ8864RMN contains four macs and two phys. the two phys support the 10/100base-t/tx. all registers of macs and phys units can be managed by the control interface of spi or the smi. miim registers of the phys can be accessed through the mdc/mdio interface. eeprom can set all control registers by i 2 c controller interface for the unmanaged mode. functional diagram
micrel, inc. KSZ8864RMN september 2011 2 m9999-092011-1.4 features advanced switch features ? ieee 802.1q vlan support for up to 128 vlan groups (full-range 4096 of vlan ids). ? static mac table supports up to 32 entries. ? vlan id tag/untag options, per port basis. ? ieee 802.1p/q tag insertion or removal on a per port basis based on ingress port (egress). ? programmable rate limiting at the ingress and egress on a per port basis. ? jitter-free per packet based rate limiting support. ? broadcast storm protection with percentage control (global and per port basis). ? ieee 802.1d rapid spanning tree protocol rstp support. ? tail tag mode (1 byte added before fcs) support at port 4 to inform the processor which ingress port receives the packet. ? 1.4gbps high-performance memory bandwidth and shared memory based switch fabric with fully non- blocking configuration. ? dual mii/rmii with mac 3 sw3-mii/rmii and mac 4 sw4-mii/rmii interfaces. ? enable/disable option for huge frame size up to 2000 bytes per frame. ? igmp v1/v2 snooping (ipv4) support for multicast packet filtering. ? ipv4/ipv6 qos support. ? support unknown unicast/multicast address and unknown vid packet filtering. ? self-address filtering. comprehensive configuration register access ? serial management interface (mdc/mdio) to all phys registers and smi interface (mdc/mdio) to all registers. ? high-speed spi (up to 25mhz) and i 2 c master interface to all internal registers. ? i/0 pins strapping and eeprom to program selective registers in unmanaged switch mode. ? control registers configurable on the fly (port-priority, 802.1p/d/q, an?). qos/cos packet prioritization support ? per port, 802.1p and diffserv-based. ? 1/2/4-queue qos prioritization selection. ? programmable weighted fair queuing for ratio control. ? re-mapping of 802.1p priority field per port basis. integrated 4-port 10/100 ethernet switch ? new generation switch with five macs and five phys that are fully compliant with the ieee 802.3u standard. ? non-blocking switch fabric assures fast packet delivery by utilizing an 1k mac address lookup table and a store-and-forward architecture. ? on-chip 64kbyte memory for frame buffering (not shared with 1k unicast address table). ? full-duplex ieee 802.3x flow control (pause) with force mode option. ? half-duplex back pressure flow control. ? hp auto mdi/mdi-x and ieee auto crossover support. ? mii interface of mac supports both mac mode and phy mode. ? per port led indicators for link, activity, and 10/100 speed. ? register port status support for link, activity, full/half duplex and 10/100 speed. ? on-chip terminations and internal biasing technology for cost down and lowest power consumption. switch monitoring features ? port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or mii/rmii. ? mib counters for fully-compliant statistics gathering 34 mib counters per port. ? loop-back support for mac, phy and remote diagnostic of failure. ? interrupt for the link change on any ports. low-power dissipation: ? full-chip hardware power-down. ? full-chip software power-down and per port software power down. ? energy-detect mode support <0.1w full-chip power consumption when all ports have no activity. ? very-low full-chip power consumption (<0.3w), without extra power consumption on transformers. ? dynamic clock tree shutdown feature. ? voltages: ? analog vddat 3.3v only. ? vddio support 3.3v, 2.5v and 1.8v. ? low 1.2v core power. ? 0.13um cmos technology. ? commercial temperature range: 0c to +70c. ? industrial temperature range: ?40c to +85c. ? available in 64-pin qfn, lead-free small package.
micrel, inc. KSZ8864RMN september 2011 3 m9999-092011-1.4 applications ? typical ? voip phone ? set-top/game box ? automotive ? industrial control ? iptv pof ? soho residential gateway ? broadband gateway / firewall / vpn ? integrated dsl/cable modem ? wireless lan access point + gateway ? standalone 10/100 switch ordering information part number temperature range package lead finish/grade KSZ8864RMN 0 c to 70 c 64-pin qfn pb-free/commercial KSZ8864RMNi ? 40 c to ? 85 c 64-pin qfn pb-free/industrial revision history revision date description 1.0 10/29/10 intiial document created. 1.1 12/16/10 correct ty po issue and others. 1.2 01/20/11 update ordering informa tion and junction thermal data. 1.3 03/18/11 update the re gisters numbers, descriptions and typo error. 1.4 07/28/11 update some descriptions of mdc/mdio smi mode and igmp, update the port register status 2 default va lue from 0x00 to 0x01 and a test register 191 default value from 0x00 to 0x80. remove the note for ordering information table.
micrel, inc. KSZ8864RMN september 2011 4 m9999-092011-1.4 contents pin confi guration .............................................................................................................. ............................................13 pin descr iption ................................................................................................................ ..............................................14 pin for strap- in op tions....................................................................................................... .........................................19 introduc tion ................................................................................................................... ................................................22 functional overview: physi cal layer tr ansceiver ................................................................................ ....................22 100base-tx tr ansmit ............................................................................................................ ...................................22 100base-tx re ceive ............................................................................................................. ...................................22 pll clock synthesizer.......................................................................................................... ......................................22 scrambler/de-scrambl er (100base-tx only)....................................................................................... .....................23 10base-t tr ansmit .............................................................................................................. ......................................23 10base-t re ceive ............................................................................................................... ......................................23 mdi/mdi-x auto crossover ....................................................................................................... .................................23 straight cable ................................................................................................................. ........................................24 crossover cable ................................................................................................................ .....................................25 auto-negot iation ............................................................................................................... ..........................................25 on-chip terminat ion resistors .................................................................................................. ................................27 functional overview: power management .......................................................................................... .......................27 normal oper ation mode .......................................................................................................... ...................................27 energy dete ct mode ............................................................................................................. ......................................27 soft power-do wn mode........................................................................................................... ...................................28 power savi ng mode.............................................................................................................. ......................................28 port-based powe r-down mode ..................................................................................................... .............................28 functional overview : switch core ............................................................................................... ...............................28 address look-up ................................................................................................................ ........................................28 learning ....................................................................................................................... ...............................................28 migration ...................................................................................................................... ...............................................28 aging.......................................................................................................................... .................................................29 forwarding ..................................................................................................................... .............................................29 switching engine ............................................................................................................... .........................................29 media access controll er (mac) o peration ........................................................................................ ........................29 inter-packet gap (ipg) ......................................................................................................... ......................................29 backoff al gorithm.............................................................................................................. ..........................................29 late collision ................................................................................................................. .............................................29 illegal frames ................................................................................................................. ............................................29 flow c ontrol................................................................................................................... .............................................29 half-duplex ba ck pressure...................................................................................................... ...................................32 broadcast storm protection..................................................................................................... ...................................32 mii interface operation ........................................................................................................ .......................................32 switch mac3/mac4 sw3/ sw4-mii interface ......................................................................................... ...................33 switch mac3/mac4 sw3/ sw4-rmii interface........................................................................................ ..................34 advanced func tionality......................................................................................................... .......................................36 qos priority support ........................................................................................................... ........................................36
micrel, inc. KSZ8864RMN september 2011 5 m9999-092011-1.4 port-based priority............................................................................................................ ......................................36 802.1p-based priority .......................................................................................................... ...................................36 diffserv-bas ed prio rity ........................................................................................................ ...................................37 spanning tree support.......................................................................................................... .....................................37 rapid spanning tr ee support .................................................................................................... ................................38 tail taggi ng m ode .............................................................................................................. ........................................39 igmp support ................................................................................................................... ..........................................40 port mirror ing support ......................................................................................................... .......................................40 vlan support ................................................................................................................... ..........................................40 rate limiti ng support .......................................................................................................... .......................................41 ingress rate limit............................................................................................................. ......................................41 egress rate limit .............................................................................................................. .....................................42 transmit queue ra tio programming............................................................................................... .......................42 filtering for self-address, unknown unicast/multicast address an d unknown vid packet/ip multicast ..................42 configuration interf ace ........................................................................................................ .......................................42 i 2 c master serial bu s configuration.............................................................................................. .........................42 spi slave serial bu s configuration ............................................................................................. ...........................43 mii management inte rface (miim) ................................................................................................ ..............................46 serial management interface (smi).............................................................................................. ..............................46 register de scription ........................................................................................................... ..........................................48 global regi sters ............................................................................................................... ..........................................50 register 0 (0x00): chip id0 .................................................................................................... ................................50 register 1 (0x01): revisi on id / start switch .................................................................................. .......................50 register 2 (0x02): global c ontrol 0 ............................................................................................ ............................50 register 3 (0x03): global c ontrol 1 ............................................................................................ ............................51 register 4 (0x04): global c ontrol 2 ............................................................................................ ............................52 register 5 (0x05): global c ontrol 3 ............................................................................................ ............................53 register 6 (0x06): global c ontrol 4 ............................................................................................ ............................54 register 7 (0x07): global c ontrol 5 ............................................................................................ ............................55 register 8 (0x08): global c ontrol 6 ............................................................................................ ............................55 register 9 (0x09): global c ontrol 7 ............................................................................................ ............................55 register 10 (0x0a): global cont rol 8........................................................................................... ...........................56 register 11 (0x0b): global cont rol 9........................................................................................... ...........................56 register 12 (0x0c): global cont rol 10 .......................................................................................... .........................57 register 13 (0x0d): global cont rol 11 .......................................................................................... .........................57 register 14 (0x0e): power do wn management control 1 ............................................................................ .........57 register 15 (0x0f): power do wn management control 2............................................................................ ..........58 port registers ................................................................................................................. ............................................59 register 16 (0x1 0): reserved................................................................................................... ..............................59 register 32 (0x20): port 1 c ontrol 0........................................................................................... ............................59 register 48 (0x30): port 2 c ontrol 0........................................................................................... ............................59 register 64 (0x40): port 3 c ontrol 0........................................................................................... ............................59 register 80 (0x50): port 4 c ontrol 0........................................................................................... ............................59
micrel, inc. KSZ8864RMN september 2011 6 m9999-092011-1.4 register 17 (0x1 1): reserved................................................................................................... ..............................60 register 33 (0x21): port 1 c ontrol 1........................................................................................... ............................60 register 49 (0x31): port 2 c ontrol 1........................................................................................... ............................60 register 65 (0x41): port 3 c ontrol 1........................................................................................... ............................60 register 81 (0x51): port 4 c ontrol 1........................................................................................... ............................60 register 18 (0x1 2): reserved................................................................................................... ..............................61 register 34 (0x22): port 1 c ontrol 2........................................................................................... ............................61 register 50 (0x32): port 2 c ontrol 2........................................................................................... ............................61 register 66 (0x42): port 3 c ontrol 2........................................................................................... ............................61 register 82 (0x52): port 4 c ontrol 2........................................................................................... ............................61 register 19 (0x1 3): reserved................................................................................................... ..............................62 register 35 (0x23): port 1 c ontrol 3........................................................................................... ............................62 register 51 (0x33): port 2 c ontrol 3........................................................................................... ............................62 register 67 (0x43): port 3 c ontrol 3........................................................................................... ............................62 register 83 (0x53): port 4 c ontrol 3........................................................................................... ............................62 register 20 (0x1 4): reserved................................................................................................... ..............................62 register 36 (0x24): port 1 c ontrol 4........................................................................................... ............................62 register 52 (0x34): port 2 c ontrol 4........................................................................................... ............................62 register 68 (0x44): port 3 c ontrol 4........................................................................................... ............................62 register 84 (0x54): port 4 c ontrol 4........................................................................................... ............................62 register 87 (0x57): rmii m anagement contro l register ........................................................................... ............63 register 25 (0x1 9): reserved................................................................................................... ..............................63 register 41 (0x29): port 1 status 0 ............................................................................................ ............................63 register 57 (0x39): port 2 status 0 ............................................................................................ ............................63 register 73 (0x49): port 3 status 0 for spd/dpx ................................................................................ ..................63 register 89 (0x59): port 4 status 0 for spd/dpx ................................................................................ ..................63 register 26 (0x1a): reserved ................................................................................................... .............................64 register 42 (0x2a): port 1 phy special c ontrol/st atus.......................................................................... ...............64 register 58 (0x3a): port 2 phy special c ontrol/st atus.......................................................................... ...............64 register 74 (0x4a): reserved ................................................................................................... .............................64 register 90 (0x5a): reserved ................................................................................................... .............................64 register 27 (0x1b): reserved ................................................................................................... .............................64 register 43 (0x2b): reserved ................................................................................................... .............................64 register 59 (0x3b): reserved ................................................................................................... .............................64 register 75 (0x4b): reserved ................................................................................................... .............................64 register 91 (0x5b): reserved ................................................................................................... .............................64 register 28 (0x1c): reserved ................................................................................................... .............................65 register 44 (0x2c): port 1 c ontrol 5 ........................................................................................... ...........................65 register 60 (0x3c): port 2 c ontrol 5 ........................................................................................... ...........................65 register 76 (0x4c): reserved ................................................................................................... .............................65 register 92 (0x5c): reserved ................................................................................................... .............................65 register 29 (0x1d): reserved ................................................................................................... .............................66 register 45 (0x2d): port 1 c ontrol 6 ........................................................................................... ...........................66
micrel, inc. KSZ8864RMN september 2011 7 m9999-092011-1.4 register 61 (0x3d): port 2 c ontrol 6 ........................................................................................... ...........................66 register 77 (0x4d): port 3 control 6 for mac loop-back ......................................................................... .............66 register 93 (0x5d): port 4 control 6 for mac loop-back ......................................................................... .............66 register 30 (0x1e): reserved ................................................................................................... .............................67 register 46 (0x2e): port 1 status 1............................................................................................ ............................67 register 62 (0x3e): port 2 status 1............................................................................................ ............................67 register 78 (0x4e): reserved ................................................................................................... .............................67 register 94 (0x5e): reserved ................................................................................................... .............................67 register 31 (0x1 f): reserved ................................................................................................... .............................67 register 47 (0x2f): port 1 control 7 and status 2 .............................................................................. ...................67 register 63 (0x3f): port 2 control 7 and status 2 .............................................................................. ...................67 register 79 (0x4 f): reserved ................................................................................................... .............................67 register 95 (0x5 f): reserved ................................................................................................... .............................67 advanced contro l registers ..................................................................................................... ..................................69 register 104 (0x68): mac address regi ster 0 .................................................................................... ..................69 register 105 (0x69): mac address regi ster 1 .................................................................................... ..................69 register 106 (0x6a): mac address regi ster 2.................................................................................... ..................69 register 107 (0x6b): mac address regi ster 3.................................................................................... ..................69 register 108 (0x6c): mac address regi ster 4.................................................................................... ..................69 register 109 (0x6d): mac address regi ster 5 .................................................................................... .................69 register 110 (0x6e): indire ct access control 0 ................................................................................. ....................69 register 111 (0x6f): indire ct access control 1................................................................................. .....................69 register 112 (0x70): indire ct data r egister 8 .................................................................................. ......................69 register 113 (0x71): indire ct data r egister 7 .................................................................................. ......................69 register 114 (0x72): indire ct data r egister 6 .................................................................................. ......................69 register 115 (0x73): indire ct data r egister 5 .................................................................................. ......................70 register 116 (0x74): indire ct data r egister 4 .................................................................................. ......................70 register 117 (0x75): indire ct data r egister 3 .................................................................................. ......................70 register 118 (0x76): indire ct data r egister 2 .................................................................................. ......................70 register 119 (0x77): indire ct data r egister 1 .................................................................................. ......................70 register 120 (0x78): indire ct data r egister 0 .................................................................................. ......................70 register 124 (0x7c): inte rrupt status register ................................................................................. .....................70 register 125 (0x7d): inte rrupt mask register ................................................................................... .....................70 register 128 (0x80): global cont rol 12 ......................................................................................... .........................71 register 129 (0x81): global cont rol 13 ......................................................................................... .........................71 register 130 (0x82): global cont rol 14 ......................................................................................... .........................71 register 131 (0x83): global cont rol 15 ......................................................................................... .........................72 register 132 (0x84): global cont rol 16 ......................................................................................... .........................72 register 133(0x85): global control 17 .......................................................................................... .........................72 register 134 (0x86): global cont rol 18 ......................................................................................... .........................73 register 135 (0x87): global cont rol 19 ......................................................................................... .........................73 register 144 (0x90): tos prio rity control register 0 ........................................................................... .................73 register 145 (0x91): tos prio rity control register 1 ........................................................................... .................74
micrel, inc. KSZ8864RMN september 2011 8 m9999-092011-1.4 register 146 (0x92): tos prio rity control register 2 ........................................................................... .................74 register 147 (0x93): tos prio rity control register 3 ........................................................................... .................74 register 148 (0x94): tos prio rity control register 4 ........................................................................... .................74 register 149 (0x95): tos prio rity control register 5 ........................................................................... .................74 register 150 (0x96): tos prio rity control register 6 ........................................................................... .................75 register 151 (0x97): tos prio rity control register 7 ........................................................................... .................75 register 152 (0x98): tos prio rity control register 8 ........................................................................... .................75 register 153 (0x99): tos prio rity control register 9 ........................................................................... .................75 register 154 (0x9a): tos prio rity control register 10.......................................................................... ................75 register 155 (0x9b): tos prio rity control register 11.......................................................................... ................75 register 156 (0x9c): tos prio rity control register 12.......................................................................... ................75 register 157 (0x9d): tos prio rity control register 13.......................................................................... ................76 register 158 (0x9e): tos prio rity control register 14.......................................................................... ................76 register 159 (0x9f): tos prio rity control register 15 .......................................................................... ................76 register 176 (0xb 0): reserved .................................................................................................. ............................76 register 192 (0xc0): port 1 c ontrol 8 .......................................................................................... ..........................76 register 208 (0xd0): port 2 c ontrol 8 .......................................................................................... ..........................76 register 224 (0xe0): port 3 c ontrol 8 .......................................................................................... ..........................76 register 240 (0xf0): port 4 c ontrol 8.......................................................................................... ...........................76 register 177 (0xb 1): reserved .................................................................................................. ............................77 register 193 (0xc1): port 1 c ontrol 9 .......................................................................................... ..........................77 register 209 (0xd1): port 2 c ontrol 9 .......................................................................................... ..........................77 register 225 (0xe1): port 3 c ontrol 9 .......................................................................................... ..........................77 register 241 (0xf1): port 4 c ontrol 9.......................................................................................... ...........................77 register 178 (0xb 2): reserved .................................................................................................. ............................77 register 194 (0xc2): port 1 c ontrol 10 ......................................................................................... .........................77 register 210 (0xd2): port 2 c ontrol 10 ......................................................................................... .........................77 register 226 (0xe2): port 3 c ontrol 10 ......................................................................................... .........................77 register 242 (0xf2): port 4 c ontrol 10......................................................................................... ..........................77 register 179 (0xb 3): reserved .................................................................................................. ............................78 register 195 (0xc3): port 1 c ontrol 11 ......................................................................................... .........................78 register 211 (0xd3): port 2 c ontrol 11 ......................................................................................... .........................78 register 227 (0xe3): port 3 c ontrol 11 ......................................................................................... .........................78 register 243 (0xf3): port 4 c ontrol 11......................................................................................... ..........................78 register 180 (0xb 4): reserved .................................................................................................. ............................78 register 196 (0xc4): port 1 c ontrol 12 ......................................................................................... .........................78 register 212 (0xd4): port 2 c ontrol 12 ......................................................................................... .........................78 register 228 (0xe4): port 3 c ontrol 12 ......................................................................................... .........................78 register 244 (0xf4): port 4 c ontrol 12......................................................................................... ..........................78 register 181 (0xb 5): reserved .................................................................................................. ............................78 register 197 (0xc5): port 1 c ontrol 13 ......................................................................................... .........................78 register 213 (0xd5): port 2 c ontrol 13 ......................................................................................... .........................78 register 229 (0xe5): port 3 c ontrol 13 ......................................................................................... .........................78
micrel, inc. KSZ8864RMN september 2011 9 m9999-092011-1.4 register 245 (0xf5): port 4 c ontrol 13......................................................................................... ..........................78 register 182 (0xb 6): reserved .................................................................................................. ............................79 register 198 (0xc6): port 1 rate limi t control................................................................................. .....................79 register 214 (0xd6): port 2 rate limi t control................................................................................. .....................79 register 230 (0xe6): port 3 rate limi t control ................................................................................. .....................79 register 246 (0xf6): port 4 rate limi t control ................................................................................. .....................79 register 183 (0xb 7): reserved .................................................................................................. ............................79 register 199 (0xc7): port 1 priori ty 0 ingress li mit control 1 ................................................................. ..............79 register 215 (0xd7): port 2 priori ty 0 ingress li mit control 1 ................................................................. ..............79 register 231 (0xe7): port 3 priori ty 0 ingress li mit control 1................................................................. ...............79 register 247 (0xf7): port 4 priori ty 0 ingress li mit control 1................................................................. ...............79 register 184 (0xb 8): reserved .................................................................................................. ............................80 register 200 (0xc8): port 1 priori ty 1 ingress li mit control 2 ................................................................. ..............80 register 216 (0xd8): port 2 priori ty 1 ingress li mit control 2 ................................................................. ..............80 register 232 (0xe8): port 3 priori ty 1 ingress li mit control 2................................................................. ...............80 register 248 (0xf8): port 4 priori ty 1 ingress li mit control 2................................................................. ...............80 register 185 (0xb 9): reserved .................................................................................................. ............................80 register 201 (0xc9): port 1 priori ty 2 ingress li mit control 3 ................................................................. ..............80 register 217 (0xd9): port 2 priori ty 2 ingress li mit control 3 ................................................................. ..............80 register 233 (0xe9): port 3 priori ty 2 ingress li mit control 3................................................................. ...............80 register 249 (0xf9): port 4 priori ty 2 ingress li mit control 3................................................................. ...............80 register 186 (0x ba): reserved.................................................................................................. ............................80 register 202 (0xca): port 1 priori ty 3 ingress li mit control 4 ................................................................. ..............80 register 218 (0xda): port 2 priori ty 3 ingress li mit control 4 ................................................................. ..............80 register 234 (0xea): port 3 priori ty 3 ingress li mit control 4 ................................................................. ..............80 register 250 (0xfa): port 4 priori ty 3 ingress li mit control 4 ................................................................. ..............80 register 187 (0x bb): reserved.................................................................................................. ............................81 register 203 (0xcb): port 1 queu e 0 egress limi t contro l 1 ..................................................................... ...........81 register 219 (0xdb): port 2 queu e 0 egress limi t contro l 1 ..................................................................... ...........81 register 235 (0xeb): port 3 queu e 0 egress limi t contro l 1 ..................................................................... ...........81 register 251 (0xfb): port 4 queu e 0 egress limi t contro l 1 ..................................................................... ...........81 register 188 (0xb c): reserved.................................................................................................. ............................81 register 204 (0xcc): port 1 queu e 1 egress limi t contro l 2..................................................................... ...........81 register 220 (0xdc): port 2 queu e 1 egress limi t contro l 2..................................................................... ...........81 register 236 (0xec): port 3 queu e 1 egress limi t contro l 2 ..................................................................... ...........81 register 252 (0xfc): port 4 queu e 1 egress limi t contro l 2 ..................................................................... ...........81 register 189 (0xb d): reserved.................................................................................................. ............................81 register 205 (0xcd): port 1 queu e 2 egress limi t contro l 3..................................................................... ...........81 register 221 (0xdd): port 2 queu e 2 egress limi t contro l 3..................................................................... ...........81 register 237 (0xed): port 3 queu e 2 egress limi t contro l 3 ..................................................................... ...........81 register 253 (0xfd): port 4 queu e 2 egress limi t contro l 3 ..................................................................... ...........81 register 190 (0x be): reserved.................................................................................................. ............................82 register 206 (0xce): port 1 queu e 3 egress limi t contro l 4 ..................................................................... ...........82
micrel, inc. KSZ8864RMN september 2011 10 m9999-092011-1.4 register 222 (0xde): port 2 queu e 3 egress limi t contro l 4 ..................................................................... ...........82 register 238 (0xee): port 3 queu e 3 egress limi t contro l 4 ..................................................................... ...........82 register 254 (0xfe): port 4 queue 3 eg ress limit contro l 4 and ch ip id ......................................................... ...82 data rate selecti on table in 100bt ............................................................................................. .............................82 data rate selecti on table in 10bt .............................................................................................. ..............................83 register 191(0xbf): testing register ........................................................................................... .........................83 register 207(0xcf): port 3 control register 1 .................................................................................. ....................83 register 223(0xdf): port 3 control r egister 2 ................................................................................... ....................84 register 239(0xef): test register 3 ............................................................................................ ..........................84 register 255(0xff): testing and port 4 cont rol regi ster ........................................................................ ..............84 static mac a ddress ta ble ....................................................................................................... ....................................85 vlan table ..................................................................................................................... ...............................................88 dynamic mac ad dress table ...................................................................................................... ................................90 mib (management inform ation base) counters..................................................................................... ....................92 miim regi sters ................................................................................................................. ..............................................95 register 0h: mii cont rol....................................................................................................... .......................................95 register 1h: mii status ........................................................................................................ .......................................96 register 2h: phyid high ........................................................................................................ ..................................96 register 3h: phyid low ......................................................................................................... ..................................96 register 4h: adve rtisement ability............................................................................................. .................................96 register 5h: link partner ability .............................................................................................. ...................................97 register 1dh: rese rved ........................................................................................................ .....................................97 register 1fh: phy s pecial contro l/status ....................................................................................... ...........................98 absolute maximum ratings (1) ............................................................................................................................... .......99 operating ratings (2) ............................................................................................................................... .......................99 electrical characteristics (4, 5) ............................................................................................................................... .........99 timing di agrams ................................................................................................................ .........................................101 eeprom timing.................................................................................................................. .....................................101 mii timing..................................................................................................................... ................................................102 rmii ti ming.................................................................................................................... ...........................................104 spi timing ..................................................................................................................... ...........................................105 auto-negotiati on timi ng ........................................................................................................ ...................................107 mdc/mdio timing................................................................................................................ ....................................108 reset timing................................................................................................................... ..........................................109 reset circui t diagram.......................................................................................................... .................................110 selection of isolation transformer (1) .........................................................................................................................111 selection of refe rence crystal ................................................................................................. .................................111 package info rmation ............................................................................................................ .......................................112
micrel, inc. KSZ8864RMN september 2011 11 m9999-092011-1.4 list of figures figure 1. typical stra ight cable connection ................................................................................... ............................ 24 figure 2. typical cros sover cable connection .................................................................................. ......................... 25 figure 3. auto -negotiation .................................................................................................... ....................................... 26 figure 4. destinat ion address loo kup flow ch art, st age 1 ...................................................................... .................. 30 figure 5. destinati on address resolution flow chart ? stage 2................................................................. ................ 31 figure 6. 802.1p prio rity fiel d format........................................................................................ .................................. 37 figure 7. tail t ag frame format ................................................................................................ .................................. 39 figure 8. KSZ8864RMN eeprom configuration ti ming diagram ...................................................................... ....... 43 figure 9. spi wri te data cycle ................................................................................................ .................................... 44 figure 10. spi r ead data cycle ................................................................................................ .................................. 44 figure 11. spi multiple write ................................................................................................. ...................................... 45 figure 12. spi multiple read .................................................................................................. ..................................... 45 figure 13. eeprom interface i nput receive timi ng diagram...................................................................... ............ 101 figure 14. eeprom interface outp ut transmit ti ming diagram.................................................................... .......... 101 figure 15. mac mode mii timing ? data receiv ed from mii ........................................................................ ............. 102 figure 16. mac mode mii timing ? data transmitte d from mii ..................................................................... ............ 102 figure 17. phy mode mii timing ? data receiv ed from mii........................................................................ .............. 103 figure 18. phy mode mii timing ? data transmitte d from mii..................................................................... ............. 103 figure 19. rmii timing ? da ta received from rmii .............................................................................. .................... 104 figure 20. rmii timing ? da ta transmitted to rmii ............................................................................. ..................... 104 figure 21. spi input timing ................................................................................................... .................................... 105 figure 22. spi output timing.................................................................................................. ................................... 106 figure 23: auto-n egotiation timing ............................................................................................ ............................... 107 figure 24. mdc/ mdio timing.................................................................................................... ................................ 108 figure 25. re set timing ....................................................................................................... ...................................... 109 figure 26. recommen ded reset circuit .......................................................................................... .......................... 110 figure 27. recommended circuit for interfacing with cpu/fpga reset............................................................ ...... 110
micrel, inc. KSZ8864RMN september 2011 12 m9999-092011-1.4 list of tables table 1. mdi/mdi- x pin defi nitions ............................................................................................ ................................. 23 table 2. internal fu nction block status ........................................................................................ ................................ 27 table 3. switch mac 3 sw3- mii and mac 4 sw4- mii signals ...................................................................... ........... 33 table 4. mac3 sw3-rmii and mac4 sw4-rm ii connection........................................................................... .......... 35 table 5. tail tag rules ........................................................................................................ ......................................... 39 table 6. fid+da look -up in the vlan mode ...................................................................................... ....................... 41 table 7. fid+sa look-up in the vl an mode...................................................................................... ........................ 41 table 8. spi connections ...................................................................................................... ...................................... 44 table 9. mii management interface fr ame format ................................................................................ ..................... 46 table 10. serial management interface (smi) frame fo rmat ...................................................................... ............... 46 table 11. 100bt rate sele ction for the rate limit............................................................................. .......................... 82 table 12. 10bt rate select ion for the ra te limit.............................................................................. .......................... 83 table 13. static mac address table ............................................................................................ ............................... 86 table 14. vl an table .......................................................................................................... ........................................ 88 table 15. vlan id and indirect registers ...................................................................................... ............................. 89 table 16. dynamic mac address table ........................................................................................... ........................... 90 table 17. port-1 mib counte r indirect memo ry offsets.......................................................................... ..................... 92 table 18. format of ?per port? mib counter .................................................................................... ............................ 93 table 19. all port dropp ed packet mib counters................................................................................ ........................ 93 table 20. format of ?all dropped packet? mib counter .......................................................................... .................... 93 table 21. eeprom timing parameters ............................................................................................ ........................ 101 table 22. mac mode m ii timing parameters...................................................................................... ...................... 102 table 23. phy mode m ii timing parameters ...................................................................................... ...................... 103 table 24. rmii ti ming parameters .............................................................................................. .............................. 104 table 25. spi input timing pa rameters ......................................................................................... ............................ 105 table 26. spi output timing pa rameters ........................................................................................ .......................... 106 table 27. auto-negotiati on timing pa rameters.................................................................................. ....................... 107 table 28. mdc/mdio ty pical timing parameters.................................................................................. ................... 108 table 29. reset timing parameters ............................................................................................. ............................. 109 table 30. transformer selection criteria ...................................................................................... ............................. 111 table 31. qualifi ed magnetic vendors .......................................................................................... ............................. 111 table 32. typical referenc e crystal characteristics ........................................................................... ...................... 111
micrel, inc. KSZ8864RMN september 2011 13 m9999-092011-1.4 pin configuration 64-pin qfn
micrel, inc. KSZ8864RMN september 2011 14 m9999-092011-1.4 pin description pin number pin name type (1) port pin function (2) 1 rxp1 i 1 physical receive signal + (differential). 2 rxm1 i 1 physical receive signal ? (differential). 3 txp1 o 1 physical transmit signal + (differential). 4 txm1 o 1 physical transmit signal ? (differential). 5 vdda12 p 1.2v analog power. 6 gnd gnd ground with all grounding of die bottom. 7 iset set physical transmit output current. pull-down with a 12.4k ? 1% resistor. 8 vddat p 3.3v analog v dd . 9 rxp2 i 2 physical receive signal + (differential). 10 rxm2 i 2 physical receive signal - (differential). 11 txp2 o 2 physical transmit signal + (differential). 12 txm2 o 2 physical transmit signal ? (differential). 13 vddat p 3.3v analog v dd . 14 intr_n opu interrupt. this pin is op en-drain output pin. 15 vddc p 1.2v digital core v dd . 16 sm3txen ipd 3 mac3 switch mii/rmii transmit enable. 17 sm3txd3 ipd 3 mac3 switch mii transmit bit 3. 18 sm3txd2 ipd 3 mac3 switch mii transmit bit 2. 19 sm3txd1 ipd 3 mac3 switch mii/rmii transmit bit 1. 20 sm3txd0 ipd 3 mac3 switch mii/rmii transmit bit 0. 21 sm3txc/sm3refclk i/o 3 mac3 switch mii transmit clock: input: sw3-mii mac mode. output: sw3-mii phy mode. input: sw3-rmii reference clock. 22 vddio p 3.3v, 2.5v or 1.8v digital v dd for digital i/o circuitry. 23 sm3rxc i/o 3 mac3 switch mii receive clock: input: sw3-mii mac mode. output: sw3-mii phy mode. output: sw3-rmii reference clock. unused rmii clock can be pull-down or disable by register 87. 24 sm3rxdv/sm3crsdv ipd/o 3 sm3rxdv: mac3 switch sw3-mii receive data valid. sm3crsdv: mac3 switch sw3-rmii carrier sense/receive data valid. 25 sm3rxd3 ipd/o 3 mac3 switch mii receive bit 3. strap option: pd (default) = enable flow control; pu = disable flow control.
micrel, inc. KSZ8864RMN september 2011 15 m9999-092011-1.4 pin number pin name type (1) port pin function (2) 26 sm3rxd2 ipd/o 3 mac3 switch mii receive bit 2 and strap option: pd (default) = disable back pressure; pu = enable back pressure. 27 sm3rxd1 ipd/o 3 mac3 switch mii/rmii receive bit 1. strap option: pd (default) = drop excessive collision packets; pu = does not drop excessive collision packets. 28 sm3rxd0 ipd/o 3 mac3 switch mii/rmii receive bit 0. strap option: pd (default) = disable aggressive back-off algorithm in half- duplex mode; pu = enable for performance enhancement. 29 sm3crs ipd/o 3 mac3 switch mii carrier sense. 30 gnd gnd ground with all grounding of die bottom. 31 sm3col ipd/o 3 mac3 switch mii collision detect. 32 sm4txen ipd 4 mac4 switch mii/rmii transmit enable. 33 sm4txd3 ipd 4 mac4 switch mii transmit bit 3. 34 sm4txd2 ipd 4 mac4 switch mii transmit bit 2. 35 sm4txd1 ipd 4 mac4 switch mii/rmii transmit bit 1. 36 sm4txd0 ipd 4 mac4 switch mii/rmii transmit bit 0. 37 sm4txc/sm4refclk i/o 4 mac4 switch mii transmit clock: input: sw4-mii mac mode clock. input: sw4-rmii reference clock, please also see the strap-in pin p1led1 for the clock mode and normal mode. output: sw4-mii phy modes. 38 vddio p 3.3v, 2.5v or 1.8v digital v dd for digital i/o circuitry. 39 sm4rxc i/o 4 mac4 switch mii receive clock: input: sw4-mii mac mode. output: sw4-mii phy mode. output: sw4-rmii 50mhz reference clock (the device is default clock mode, the clock source comes from x1/x2 pins 25mhz crystal). when set the device as normal mode (the chip?s clock source comes from sm4txc), the sm4rxc reference clock output should be disabled by the register 87. please also see the strap-in pin p1led1 for the se lection of the clock mode and normal mode. 40 sm4rxdv/sm4crsdv ipd/o 4 sm4rxdv: mac4 switch sw4-mii receive data valid. sm4crsdv: mac4 switch sw4-rmii carrier sense/receive data valid
micrel, inc. KSZ8864RMN september 2011 16 m9999-092011-1.4 pin number pin name type (1) port pin function (2) 41 sm4rxd3 ipd/o 4 mac4 switch mii receive bit 3. strap option: pd (default) = disable switch m ii/rmii full-duplex flow control; pu = enable switch mii/rmii full-duplex flow control. 42 sm4rxd2 ipd/o 4 mac4 switch mii receive bit 2. strap option: pd (default) = switch mii/rmii in full-duplex mode; pu = switch mii/rmii in half-duplex mode. 43 sm4rxd1 ipd/o 4 mac4 switch mii/rmii receive bit 1. strap option: pd (default) =mac4 switch sw 4-mii/rmii in 100mbps mode; pu = mac4 switch sw-5mii/rmii in 10mbps mode. mac4 switch mii/rmii receive bit 0. strap option: led mode pd (default) = mode 0; pu = mode 1. see ?register 11.? mode 0 mode 1 pxled1 lnk/act 100lnk/act 44 sm4rxd0 ipd/o 4 pxled0 speed full duplex 45 sm4col ipd/o 4 mac4 switch mii collision detect: input: sw4-mii mac modes. output: sw4-mii phy modes. 46 sm4crs ipd/o 4 mac4 switch mii modes carrier sense: input: sw4-mii mac modes. output: sw4-mii phy modes. mac4 switch sw4-mii enabled with phy mode or mac mode, have to configure sconf1 pin 47 with sconf0 pin 48 together. see pins configutation table below: pin# (47,48) port 4 switch mac4 sw4- mii 00 (default) sw4-mii phy mode 01 disabled 10 disabled 47 sconf1 ipd 11 sw4-mii mac mode 48 sconf0 ipd port 4 switch sw4-mii enabled with phy mode or mac mode, have to configure sconf0 pin 48 with sconf1 pin 47 together. see pin 47 description. 49 p2led1 ipu/o 2 led indicator for port 2. this pin has to be pulled down by 1k resistor in the design for KSZ8864RMN.
micrel, inc. KSZ8864RMN september 2011 17 m9999-092011-1.4 pin number pin name type (1) port pin function (2) 50 p2led0 ipu/o 2 led indicator for port 2. strap option: switch mac3 used only. pu (default) = select mii interface for the switch mac3 sw3- mii. pd = select rmii interface fo r the switch mac3 sw3-rmii. 51 p1led1 ipu/o 1 led indicator for port 1. strap option: switch rmii used only. pu (default) = select the device as clock mode, when use rmii interface, all clock source come from pin x1/x2 crystal 25mhz. pd = select the device as normal mode when use rmii interface. all clock source comes from sw4-rmii sm4txc pin with an external input 50mhz clock. in the normal mode, the 25mhz crystal clock from pin x1/x2 doesn?t take affect and should disable sw4-rmii sw4rxc 50mhz clock output by the register 87. the normal mode is used when sw4-rmii receive an external 50mhz rmii reference clock from pin sm4txc. 52 p1led0 ipu/o 1 led indicator for port 1. strap option: for switch mac4 only. pu (default) = select mii interface for the switch mac4 sw4- mii. pd = select rmii interface fo r the switch mac4 sw4-rmii. 53 mdc ipu all mii management interface clock. or smi interface clock 54 mdio ipu/o all mii management data i/o. or smi interface data i/o features internal pull down to define pin state when not driven. note: need an external pull-up when driven. 55 spiq ipu/o all spi serial data output in spi slave mode. note: need an external pull-up when driven. 56 spic/scl ipu/o all (1) input clock up to 25mhz in spi slave mode, (2) output clock at 61khz in i 2 c master mode. note: need an external pull-up when driven. 57 spid/sda ipu/o all (1) serial data input in spi slave mode; (2) serial data input/output in i 2 c master mode. note: need an external pull-up when driven. 58 spis_n ipu all active low. (1) spi data transfer start in spi slave mode. when spis_n is high, the device is deselected and spiq is held in high impedance state, a high-to-low trans ition to initiate the spi data transfer. (2) not used in i 2 c master mode.
micrel, inc. KSZ8864RMN september 2011 18 m9999-092011-1.4 pin number pin name type (1) port pin function (2) serial bus configuration pin. for this case, if the eeprom is not present, the switch will start itself with the ps[1.0] = 00 default register values. pin configuration serial bus configuration ps[1.0]=00 i 2 c master mode for eeprom ps[1.0]=01 smi interface mode ps[1.0]=10 spi slave mode for cpu interface 59 ps1 ipd ps[1.0]=11 factory test mode (bist) 60 ps0 ipd serial bus configuration pin. 61 rst_n ipu reset the device. active low. 62 vddc p 1.2v digital core v dd . 63 x1 i 25mhz crystal clock connection/or 3.3v oscillator input. crystal/oscillator should be <= 50ppm tolerance. 64 x2 o 25mhz crystal clock connection. notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect. 2. pu = strap pin pull-up. pd = strap pull-down. otri = output tristated.
micrel, inc. KSZ8864RMN september 2011 19 m9999-092011-1.4 pin for strap-in options the KSZ8864RMN can function as a managed switch or unmanaged switch. if no eeprom or micro-controller exists, the KSZ8864RMN will operate from its default setting. the strap-in option pins can be configures by external pull-up/down resistors and take the effect after power up reset or warm reset, the functions are described in the following table: pin number pin name type (1) port pin function (2) 25 sm3rxd3 ipd/o mac3 switch mii receive bit 3 strap option: pd (default) = enable flow control; pu = disable flow control. 26 sm3rxd2 ipd/o mac3 switch mii receive bit 2 and strap option: pd (default) = disable back pressure; pu = enable back pressure. 27 sm3rxd1 ipd/o mac3 switch mii/rmii receive bit 1 strap option: pd (default) = drop excessive collision packets; pu = does not drop excessive collision packets. 28 sm3rxd0 ipd/o mac3 switch mii/rmii receive bit 0 strap option: pd (default) = disable aggressive back-off algorithm in half-duplex mode; pu = enable for performance enhancement. 41 sm4rxd3 ipd/o mac4 switch mii receive bit 3. strap option: pd (default) = disable switch m ii/rmii full-duplex flow control; pu = enable switch mii/rmii full-duplex flow control. 42 sm4rxd2 ipd/o mac4 switch mii receive bit 2. strap option: pd (default) = switch mii/rmii in full-duplex mode; pu = switch mii/rmii in half-duplex mode. 43 sm4rxd1 ipd/o mac4 switch mii/rmii receive bit 1. strap option: pd (default) =mac4 switch sw 4-mii/rmii in 100mbps mode; pu = mac4 switch sw-5mii/rmii in 10mbps mode. mac4 switch mii/rmii receive bit 0. strap option: led mode pd (default) = mode 0; pu = mode 1. see ?register 11.? mode 0 mode 1 pxled1 lnk/act 100lnk/act 44 sm4rxd0 ipd/o pxled0 speed full duplex 47 sconf1 ipd mac4 switch sw4-mii enabled with phy mode or mac mode, have to configure sconf1 pin 47 with sconf0 pin 48 together.
micrel, inc. KSZ8864RMN september 2011 20 m9999-092011-1.4 pin number pin name type (1) port pin function (2) see pins configuration table below: pin# (47,48) switch mac4 sw4- mii/rmii 00 (default) sw4-mii phy mode 01 disabled 10 disabled 11 sw4-mii mac mode 48 sconf0 ipd port 4 switch sw4-mii enabled with phy mode or mac mode, have to configure sconf0 pin 48 with sconf1 pin 47 together. see pin 47 description. 49 p2led1 ipu/o 2 led indicator for port 2. this pin has to be pulled down by 1k resistor in the design for KSZ8864RMN. 50 p2led0 ipu/o 2 led indicator for port 2. strap option: switch mac3 used only. pu (default) = select mii interfac e for the switch mac3 sw3-mii. pd = select rmii interface fo r the switch mac3 sw3-rmii. 51 p1led1 ipu/o 1 led indicator for port 1. strap option: switch rmii used only. pu (default) = select the device as cl ock mode. when use rmii interface, all clock source come from pin x1/x2 crystal 25mhz. pd = select the device as normal mode when use rmii interface. all clock source comes from sw4-rmii sm4txc pin with an external input 50mhz clock. in the normal mode, the 25mhz crystal clock from pin x1/x2 doesn?t take affect and should disable sw4-rmii sw4rxc 50mhz clock output by the register 87. the normal mode is used when sw4-rmii receive an external 50mhz rmii reference clock from pin sm4txc. 52 p1led0 ipu/o 1 led indicator for port 1. strap option: for switch mac4 only. pu (default) = select mii interfac e for the switch mac4 sw4-mii. pd = select rmii interface fo r the switch mac4 sw4-rmii. serial bus configuration pin. for this case, if the eeprom is not pres ent, the switch will start itself with the ps[1.0] = 00 default register values. pin configuration serial bus configuration ps[1.0]=00 i 2 c master mode for eeprom ps[1.0]=01 smi interface mode ps[1.0]=10 spi slave mode for cpu interface 59 ps1 ipd ps[1.0]=11 factory test mode (bist)
micrel, inc. KSZ8864RMN september 2011 21 m9999-092011-1.4 notes: 1. p = power supply. i = input. o = output. i/o = bidirectional. gnd = ground. ipu = input w/internal pull-up. ipd = input w/internal pull-down. ipd/o = input w/internal pull-down during reset, output pin otherwise. ipu/o = input w/internal pull-up during reset, output pin otherwise. nc = no connect. 2. pu = strap pin pull-up. pd = strap pull-down. otri = output tristated.
micrel, inc. KSZ8864RMN september 2011 22 m9999-092011-1.4 introduction the KSZ8864RMN contains two 10/100 physical layer transc eivers and four media access control (mac) units with an integrated layer 2 managed switch. the device runs in mu ltiple modes. they are two copper + two mac mii, two copper + two mac rmii, two copper + 1 mac mii+ 1 ma c rmii and two copper + 1 mac mii or 1 mac rmii. those are useful for implementing multiple products in many applications. the KSZ8864RMN has the flexibility to reside in a managed or unmanaged design. in a managed design, a host processor has complete control of the KSZ8864RMN via the sp i bus, or partial control via the mdc/mdio interface. an unmanaged design is achieved th rough i/o strapping or eeprom programming at system reset time. on the media side, the ksz8864rm n supports ieee 802.3 10base-t, 100 base-tx on all ports with auto mdi/mdix. the KSZ8864RMN can be used as fully managed 4- port switch through two mi croprocessors by its two mii interface or rmii interface for an advance management application. physical signal transmission and reception are enhanced th rough the use of patented anal og circuitry with enhanced mix signal technology that makes the design more efficient and allows for lower power consumption and smaller chip die size. the major enhancements of the KSZ8864RMN is small pack age with configuble of two mii and rmii modes for two mac interfaces. the KSZ8864RMN supports more new featur es for host processor management, multiple kind of packets filtering, tag as well as port based vlan, rapid spanning tree support, igmp snooping support, port mirroring support and more flexible rate limiting and more functionality. functional overview: phys ical layer transceiver 100base-tx transmit the 100base-tx transmit function performs parallel-to-seri al conversion, 4b/5b coding, scrambling, nrz-to-nrzi conversion, mlt3 encoding and transmission. the circuit star ts with a parallel-to-serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream . the data and control stream is then converted into 4b/5b coding followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 1% 12.4k ? resistor for the 1:1 transformer ratio. it has a typical rise/fall time of 4ns and complies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-s haped 10base-t output is also incorporated into the 100base-tx transmitter. 100base-tx receive the 100base-tx receiver function performs adaptive equaliz ation, dc restoration, mlt3 -to-nrzi conversion, data and clock recovery, nrzi-to-nrz conver sion, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalizati on filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a f unction of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. in this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. this is an ongoing process and can self-adjust against environmental changes such as temperature variations. the equalized signal then goes through a dc restoration and da ta conversion block. the dc restoration circuit is used to compensate for the effect of baseline wan der and improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from t he edges of the nrzi signal. th is recovered clock is then used to convert the nrzi signal into the nrz format. t he signal is then sent through the de-scrambler followed by the 4b/5b decoder. finally, the nrz serial data is convert ed to the mii format and provided as the input data to the mac. pll clock synthesizer the KSZ8864RMN generates 125mhz, 83mhz, 41mhz, 25mhz and 10mhz clocks for system timing. internal clocks are generated from an external 25mhz crystal or oscillator.
micrel, inc. KSZ8864RMN september 2011 23 m9999-092011-1.4 scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spec trum of the signal in order to reduce emi and baseline wander. the data is scrambled through the use of an 11-bi t wide linear feedback shift register (lfsr). this can generate a 2047-bit non-repetitive sequence. the receiver w ill then de-scramble the incoming data stream with the same sequence at the transmitter. 10base-t transmit the output 10base-t driver is incorpor ated into the 100base-t driver to allow transmission with the same magnetics. they are internally wave -shaped and pre-emphasized into outputs with a typical 2.3v amplitude. the harmonic contents are at least 27db bel ow the fundamental when driven by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffer and level detecting squelch ci rcuits are employed. a differential input receiver circuit and a pll perform the decoding function. the manchester-e ncoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulsewidths in order to prevent noises at the rxp or rxm input from falsely triggering t he decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the KSZ8864RMN decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. mdi/mdi-x auto crossover to eliminate the need for crossover cables between similar devices, the KSZ8864RMN supports hp auto mdi/mdi-x and ieee 802.3u standard mdi/mdi-x auto crossover. hp auto mdi/mdi-x is the default. the auto-sense function detects remote transmit and receive pa irs and correctly assigns transmit and receive pairs for the ksz8898mq/tmq device. this feature is extremely useful when end users are unaware of cable types, and also, saves on an additional uplink configuration connection. the auto-crossover feat ure can be disabled through the port control registers, or m iim phy registers. the ieee 802.3u standar d mdi and mdi-x definitions are: mdi mdi-x rj-45 pins signals rj-45 pins signals 1 td+ 1 rd+ 2 td- 2 rd- 3 rd+ 3 td+ 6 rd- 6 td- table 1. mdi/mdi-x pin definitions
micrel, inc. KSZ8864RMN september 2011 24 m9999-092011-1.4 straight cable a straight cable connects an mdi device to an mdi-x device, or an mdi-x device to an mdi device. the following diagram depicts a typical straight cable connection be tween a nic card (mdi) and a switch, or hub (mdi-x). figure 1. typical straight cable connection
micrel, inc. KSZ8864RMN september 2011 25 m9999-092011-1.4 crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi-x device to another mdi-x device. the following diagram shows a typical crossover cable connec tion between two switches or hubs (two mdi-x devices). figure 2. typical crossover cable connection auto-negotiation the KSZ8864RMN conforms to the auto-negotiation protocol as described by the 802.3 committee. auto-negotiation allows unshielded twisted pair (utp) link partners to sele ct the highest common mode of operation. link partners advertise their capabilities to each othe r, and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is comm on to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest. ? highest: 100base-tx, full-duplex ? high: 100base-tx, half-duplex ? low: 10base-t, full-duplex ? lowest: 10base-t, half-duplex
micrel, inc. KSZ8864RMN september 2011 26 m9999-092011-1.4 if auto-negotiation is not supported or the KSZ8864RMN link partner is forced to bypass auto-negotiation, then the KSZ8864RMN sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allows the KSZ8864RMN to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. the auto-negotiation link up process is shown in the following flow chart: figure 3. auto-negotiation
micrel, inc. KSZ8864RMN september 2011 27 m9999-092011-1.4 on-chip termination resistors the KSZ8864RMN reduces board cost and simplifies board lay out by using on-chip termination resistors for rx/tx differential pairs without the external te rmination resistors. the solution of the on chip termination and internal biasing will enhance much power consumption compare with usi ng external biasing and termination resistors, and the transformer will not consume power any longer. the center tap doesn?t need to be tied to analog power, just leave them floating or connect the capacitors to ground separately. functional overview: power management the KSZ8864RMN can also use multiple power level of 3.3v, 2. 5v or 1.8v for vddio to support different i/o voltage. the KSZ8864RMN supports enhanced power management f eature in low power state with energy detection to ensure low-power dissipation during device idle perio ds. there are five operation modes under the power management function which is controlled by the register 14 bit [4:3] and the port register control 13 bit3 as shown below: register 14 bit [4:3] = 00 normal operation mode register 14 bit [4:3] = 01 energy detect mode register 14 bit [4:3] = 10 soft power down mode register 14 bit [4:3] = 11 power saving mode the port register control 13 bit 3 =1 is for the port based power-down mode table 2 indicates all internal function blocks status under four different power management operation modes. power management operation modes KSZ8864RMN function blocks normal mode power saving mode energy detect mode soft power down mode internal pll clock enabled enabled disabled disabled tx/rx phy enabled rx unused block disabled energy detect at rx disabled mac enabled enabled disabled disabled host interface enabled enabled disabled disabled table 2. internal function block status normal operation mode this is the default setting bit [4:3] =00 in register 14 after the chip power-up or hardware reset. when KSZ8864RMN is in this normal operation mode, all pll clocks are runni ng, phy and mac are on and the host interface is ready for cpu read or write. during the normal operation mode, the host cpu can set the bit [4:3] in register 14 to transit the current normal operation mode to any one of the other th ree power management operation modes. energy detect mode the energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8864RMN is not connected to an active link partner. in this mode, if the cable is not plugged, then the KSZ8864RMN can automatically enter to a low power st ate, i.e., the energy detect mode. in this mode, KSZ8864RMN will keep transmitting 120ns width pulses at 1 pulse/s rate. once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8864RMN can automatically power up to normal power state in energy detect mode.
micrel, inc. KSZ8864RMN september 2011 28 m9999-092011-1.4 energy detect mode consists of two states, normal power st ate and low power state. while in low power state, the KSZ8864RMN reduces power consumption by disabling all circui try except the energy detect circuitry of the receiver. the energy detect mode is entered by setting bit [4:3] = 01 in register 14. when the KSZ8864RMN is in this mode, it will monitor the cable energy. if there is no energy on the ca ble for a time longer than pre-configured value at bit [7:0] go-sleep time in register 15, then the KSZ8864RMN will go into a low power state. when KSZ8864RMN is in low power state, it will keep monitoring the cable energy. on ce the energy is detected from the cable, KSZ8864RMN will enter normal power state. when KSZ8864RMN is at normal power state, it is able to transmit or receive packet from the cable. soft power-down mode the soft power-down mode is entered by setting bit [4:3] = 10 in register 14. when KSZ8864RMN is in this mode, all pll clocks are disabled, also all of phys and the macs are off. any dummy host acce ss will wake-up this device from current soft power down mode to normal operation mode and internal reset will be issued to make all internal registers go to the default values. power saving mode the power saving mode is entered when auto-negotiation m ode is enabled, cable is disconnected, and by setting bit [4:3] =11 in register 14. when KSZ8864RMN is in this m ode, all pll clocks are enabled, mac is on, all internal registers value will not change, and host interf ace is ready for cpu read or write. in this mode, it mainly controls the phy transceiver on or off based on line status to achieve power saving. the phy remains transmitting and only turns off the unused receiver block. once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8864RMN can automatically enabled the phy power up to normal pow er state from power saving mode. during this power saving mode, the host cpu can set bit [4:3 ] in register 14 to transit the current power saving mode to any one of the other three power management operation modes. port-based power-down mode in addition, the KSZ8864RMN features a per-port power down mode. to save power, a phy port that is not in use can be powered down by the port registers cont rol 13 bit3, or miim phy registers 0 bit11. functional overview: switch core address look-up the internal look-up table stores ma c addresses and their associ ated information. it contains a 1k unicast address table plus switching information. the KSZ8864RMN is gua ranteed to learn 1k addresses and distinguishes itself from a hash-based look-up table which, depending upon the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. learning the internal look-up engine updates its table with a new entry if the following conditions are met: ? the received packet?s source address ( sa) does not exist in the look-up table. ? the received packet is good; the packet has no receiving errors and is of legal length. the look-up engine inserts the qualified sa into the table, along with the port number and time stamp. if the table is full, the last entry of the table is delet ed first to make room for the new entry. migration the internal look-up engine also monito rs whether a station is moved. if this occurs, it updates the table accordingly. migration happens when the following conditions are met: ? the received packet?s sa is in the table but t he associated source port information is different. ? the received packet is good; the packet has no receiving errors and is of legal length. the look-up engine will updat e the existing record in the table with the new source port information.
micrel, inc. KSZ8864RMN september 2011 29 m9999-092011-1.4 aging the look-up engine will update the time stamp information of a record whenever the corresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of time, the look-up engine will remove the record from the table. the look-up engine co nstantly performs the aging process and will continuously remove aging records. the aging period is 300 +/- 75 seconds. this feature can be enabled or disabled through register 3. see ?register 3? section. forwarding the KSZ8864RMN will forward packets using an algorithm th at is depicted in the fo llowing flowcharts. figure 6 shows stage one of the forwarding algor ithm where the search engine looks up the vlan id, static table, and dynamic table for the destination address, and comes up with ?port to forward 1? (ptf1). ptf1 is then further modified by the spanning tree, igmp snooping, port mirroring, and port vlan processes to come up with ?port to forward 2? (ptf2), as shown in figure 7. this is wh ere the packet will be sent. KSZ8864RMN will not forward the following packets : ? error packets. these include framing errors, fcs erro rs, alignment errors, and illegal size packet errors. ? 802.3x pause frames. the KSZ8864RMN will intercept t hese packets and perform the appropriate actions. ? ?local? packets. based on destination address (da) l ook-up. if the destination port from the look-up table matches the port where the packet was from , the packet is defined as ?local.? switching engine the KSZ8864RMN features a high-perf ormance switching engine to move dat a to and from the mac?s, packet buffers. it operates in store and forward mode, while the effi cient switching mechanism reduces overall latency. the KSZ8864RMN has a 64kb internal frame buffer. this resource is shared between all five ports. there are a total of 512 buffers available. each buffer is sized at 128b. media access controller (mac) operation the KSZ8864RMN strictly abides by ieee 802. 3 standards to maximize compatibility. inter-packet gap (ipg) if a frame is successfully transmitted, the 96-bit time ip g is measured between the two consecutive mtxen. if the current packet is experiencing collision, the 96-bit ti me ipg is measured from mcrs and the next mtxen. backoff algorithm the KSZ8864RMN implements the ieee std. 802.3 binary ex ponential back-off algorithm , and optional ?aggressive mode? back off. after 16 collisions, t he packet will be optionally dropped depen ding on the chip configuration in register 3. see ?register 3.? late collision if a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. illegal frames the KSZ8864RMN discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in register 4. for special applications, the KSZ8864RMN ca n also be programmed to accept frames up to 1916 bytes in register 4. since the KSZ8864RMN supports vlan t ags, the maximum sizing is adjusted when these tags are present. flow control the KSZ8864RMN supports standard 802.3x flow cont rol frames on both transmit and receive sides. on the receive side, if the KSZ8864RMN receives a pause control frame, the ksz8864rm n will not transmit the next normal frame until the timer, specified in the pause control frame, expires. if another pause frame is received before the current timer expire s, the timer will be updated with the new value in the second pause fram e. during this period (being flow controlled), only flow control pac kets from the KSZ8864RMN will be transmitted.
micrel, inc. KSZ8864RMN september 2011 30 m9999-092011-1.4 on the transmit side, the KSZ8864RMN has intelligent and effici ent ways to determine when to invoke flow control. the flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. the KSZ8864RMN flow controls a port that has just receiv ed a packet if the destination port resource is busy. the KSZ8864RMN issues a flow control fr ame (xoff), containing the maximum pause time defined in ieee standard 802.3x. once the resource is freed up, the KSZ8864RMN send s out the other flow contro l frame (xon) with zero pause time to turn off the flow control (turn on transmissi on to the port). a hysteresis feature is also provided to prevent over-activation and deactivation of the flow control mechanism. the KSZ8864RMN flow controls all ports if the receive queue becomes full. figure 4. destination address lookup flow chart, stage 1
micrel, inc. KSZ8864RMN september 2011 31 m9999-092011-1.4 figure 5. destination address resolution flow chart ? stage 2
micrel, inc. KSZ8864RMN september 2011 32 m9999-092011-1.4 the KSZ8864RMN will not forw ard the following packets: 1. error packets. these include framing errors, frame check sequence (f cs) errors, alignment errors, and illegal size packet errors. 2. ieee802.3x pause frames . KSZ8864RMN intercepts these packets and perform s full duplex flow control accordingly. 3. "local" packets . based on destination address (da) lookup, if the destinati on port from the lookup table matches the port from which the packet originated, the packet is defined as "local." half-duplex back pressure the KSZ8864RMN also provides a half-duplex back pressure opt ion (note: this is not lis ted in ieee 802.3 standards). the activation and deactivation conditions are the same as the ones given for full-duplex mode. if back pressure is required, the KSZ8864RMN sends preambles to defer the othe r station's transmission (carrier sense deference). to avoid jabber and excessive def erence as defined in i eee 802.3 standard, after a ce rtain period of time, the KSZ8864RMN discontinues carrier sense but raises it quickly after it drops packets to inhibit other transmissions. this short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in a carrier sense deferred state. if the port has pa ckets to send during a back pre ssure situation, the carrier- sense-type back pressure is interrupted and those packets are transmitted instead. if there are no more packets to send, carrier-sense-type back pressure becomes active again until switch resources are free. if a collision occurs, the binary exponential backoff algorithm is skipped and carrier se nse is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets.to ensur e no packet loss in 10base-t or 100base-tx half-duplex modes, the user must enable the following: ? aggressive backoff (register 3, bit 0) ? no excessive collision dr op (register 4, bit 3) ? back pressure (register 4, bit 5) these bits are not set as the default be cause this is not the ieee standard. broadcast storm protection the KSZ8864RMN has an intelligent option to protect the swit ch system from receiving t oo many broadcast packets. broadcast packets are normally forwarded to all ports except the source port and thus use too many switch resources (bandwidth and available space in transmit queues). the KSZ8864RMN has the option to include ?multicast packets? for storm contro l. the broadcast storm rate parameter s are programmed globally and can be enabled or disabled on a per port basis. the rate is based on a 50ms interval for 100bt and a 500ms interval for 10bt. at the beginning of each interval, t he counter is cleared to zeroand the rate limit mechanism starts to count the number of bytes during the interval. the rate definition is described in registers 6 and 7. the default setting for registers 6 and 7 is 0 x 4 a (74 decimal). this is equal to a rate of 1%, calculated as follows: 148,800 frames/sec 50ms/interval 1% = 74 frames/interval (approx.) = 0x4a. mii interface operation the media independent interface (mii) is specified by the ieee 802.3 commi ttee and provides a common interface between physical layer and mac layer devices. the ksz8864 rmn provides two mac layer interfaces for mac 3 and mac 4. each of these mii/rmii interf aces contains two distin ct groups of signals, o ne for transmission and the other for receiving.
micrel, inc. KSZ8864RMN september 2011 33 m9999-092011-1.4 switch mac3/mac4 sw3/sw4-mii interface table 3 shows two connection manners, 1. the first is an external mac connects to sw3/sw4-mii phy mode. 2. the second is an external phy connects to sw3/sw4-mii mac mode. please see the pins [47, 48] description for detail configur ation for the mac mode and phy mode of the port 4 mac4 sw4-mii, the default is sw4-mii with ph y mode. please see the strap pin p2led0 and the register 223 bit 6 for the mac mode and phy mode of the port 3 mac3 sw3- mii, the default is sw3-mii with phy mode also. KSZ8864RMN phy mode connection KSZ8864RMN mac mode connection external mac KSZ8864RMN sw3/4-mii signals type description external phy KSZ8864RMN sw3/4-mii signals type mtxen smxtxen input transmit enable mtxen smxrxdv output mtxd3 smxtxd[3] input transmit data bit 3 mtxd3 smxrxd[3] output mtxd2 smxtxd[2] input transmit data bit 2 mtxd2 smxrxd[2] output mtxd1 smxtxd[1] input transmit data bit 1 mtxd1 smxrxd[1] output mtxd0 smxtxd[0] input transmit data bit 0 mtxd0 smxrxd[0] output mtxc smxtxc output transmit clock mtxc smxrxc input mcol smxcol output collision detection mcol smxcol input mcrs smxcrs output carrier sense mcrs smxcrs input mrxdv smxrxdv output receive data valid mrxdv smxtxen input mrxd3 smxrxd[3] output receive data bit 3 mrxd3 smxtxd[3] input mrxd2 smxrxd[2] output receive data bit 2 mrxd2 smxtxd[2] input mrxd1 smxrxd[1] output receive data bit 1 mrxd1 smxtxd[1] input mrxd0 smxrxd[0] output receive data bit 0 mrxd0 smxtxd[0] input mrxc smxrxc output receive clock mrxc smxtxc input note : ?x? is 3 or 4 for sw3 or sw4 in the table. table 3. switch mac 3 sw3-mii and mac 4 sw4- mii signals
micrel, inc. KSZ8864RMN september 2011 34 m9999-092011-1.4 the switch mii interface operates in either mac mode or phy mode for KSZ8864RMN. these interfaces are nibble- wide data interfaces and therefore run at one-quarter the network bit rate (n ot encoded). additional signals on the transmit side indicate when data is valid or when an erro r occurs during transmission. likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. for half-duplex operation, there is a signal that indicates a collision has occurred during transmission. note that the signal mrxer is not provided on the swx-m ii interface and the signal mtxer is not provided on the swx-mii interface for both phy and mac mode operation. no rmally mrxer would indicate a receive error coming from the physical layer device. mtxer would indicate a tr ansmit error from the mac dev ice. these signals are not appropriate for this configuration. for phy mode operatio n, if the device interfacing with the KSZ8864RMN has an mrxer pin, it should be tied low. for mac mode operation, if the device interfacing with the KSZ8864RMN has an mtxer pin, it should be tied low. switch mac3/mac4 sw3/sw4-rmii interface the reduced media independent interface (rmii) specifie s a low pin count media independent interface (mii). the KSZ8864RMN supports rmii interface at port 3 and port 4 sw itch sides and provides a common interface at mac3 and mac4 layer in the device, and has the following key characteristics: ? supports 10mbps and 100mbps data rates. ? uses a single 50 mhz clock reference (provided internally or externally): in internal mode, the chip provides reference clock from smxrxc pin to smxtxc/smxrefclk pin and the reference cloc k-in pin of the opposite rmii; in external mode, the chip receives 50mhz referenc e clock from an external oscillator or opposite rmii interface to sw4txc/sm4refclk pin only. ? provides independent 2-bit wide (bi-bit) transmit and receive data paths. table 4 shows two types of rmii connections of mac to mac and mac to phy, ? the first is an external mac conne cts to sw3/4-rmii with ?phy mode?. ? the second is an external phy connects to sw3/4-rmii with ?mac mode?. when the strap pin p1led0 is pulled down, the switch ma c4 is sw4-rmii mode after power up reset or warm reset. when the strap pin p2led0 is pulled down, the switch mac3 is sw3-rmii mode after power up reset or warm reset.
micrel, inc. KSZ8864RMN september 2011 35 m9999-092011-1.4 sw3/4-rmii mac to mac connection (?phy? mode) sw3/4-rmii mac to phy connection (?mac? mode) external mac KSZ8864RMN signal KSZ8864RMN sw signal type description external phy KSZ8864RMN signal KSZ8864RMN sw signal type ref_clk smxrxc output (clock mode with 50mhz) reference clock ? smxtxc /smxrefclk input (clock comes from smxrxc in clock mode or external 50mhz clock) crs_dv smxrxdv /smxcrsdv output carrier sense/receive data valid crs_dv smxtxen input rxd1 smxrxd[1] output receive data bit 1 rxd1 smxtxd[1] input rxd0 smxrxd[0] output receive data bit 0 rxd0 smxtxd[0] input tx_en smxtxen input transmit data enable tx_en smxrxdv /smxcrsdv output txd1 smxtxd[1] input transmit data bit 1 txd1 smxrxd[1] output txd0 smxtxd[0] input transmit data bit 0 txd0 smxrxd[0] output (not used) (not used) receive error (not used) (not used) ? smxtxc /smxrefclk input (clock comes from smxrxc in clock mode or external 50mhz clock) reference clock ref_clk smxrxc output (clock mode with 50mhz ) note : 1. ?x? is 3 or 4 for sw3 or sw4 in the table. 2. mac/phy mode in rmii is difference with mac/phy mode in mii, there is no strap pin and register configuration request in rmi i, just follow the signals connection in the table. table 4. mac3 sw3-rmii a nd mac4 sw4-rmii connection KSZ8864RMN provides two rmii interfaces for mac3 and mac4: ? switch mac4 sw4-rmii interface can be used to provi de 50mhz clock to opposite rmii from sm4rxc pin with loop back to sm4txc pin. the sw4-rmii interface can be used to accept 50mhz from external 50mhz clock to sm4txc when KSZ8864RMN is configured to normal mode by the strap pin p1led1 pull-down. in the normal mode, the clock source of the KSZ8864RMN comes from the sm4txc. ? switch mac3 sw3-rmii interface can be used to provi de 50mhz clock to opposite rmii from sm3rxc pin with loop back to sm3txc pin. the sw3-rmii interface can not be used to accept 50mhz from external to sm3txc with the normal mode configuration.
micrel, inc. KSZ8864RMN september 2011 36 m9999-092011-1.4 the default of the device is clock mode because the p1led1 is pulled up inte rnally, the clock mode means the clock source comes from 25mhz crystal/oscillator on pins x1/x 2, and the 50mhz clock will be output from the smxrxc pin in rmii interface to be used, the 50mhz can be disabled by the register 87 bit 3 and bit 2 for sm4rxc and sm3rxc if the reference clock is not used. for the detail rmii c onnection samples, please refer to the application note in the design kit. advanced functionality qos priority support the KSZ8864RMN provides quality of service (qos) for applications such as voip and video conferencing. the KSZ8864RMN offer 1/2/4 priority queues opt ion per port by setting the port regi sters xxx control 9 bit1 and the port registers xxx control 0 bit0, the 1/2/4 queues split as follows: [port registers xxx control 9 bit1, contro l 0 bit0]=00 single output queue as default. [port registers xxx control 9 bit1, control 0 bit0]=01 egress port can be split into two priority transmit queues. [port registers xxx control 9 bit1, control 0 bit0]=10 egress port can be split into four priority transmit queues. the four priority transmit queues is a new feature in the KSZ8864RMN. the queue 3 is the highest priority queue and queue 0 is the lowest priority queue. th e port registers xxx control 9 bit1 and th e port registers xxx control 0 bit0 are used to enable split transmit queues for ports 1and 2, respecti vely. if a port's transmit queue is not split, high priority and low priority packets have equal priority in the transmit queue. there is an additional option to either always deliver high priority packets first or use programmable weighted fair queuing for the four priority queues scale by the port registers control 10, 11, 12 and 13 (default value are 8, 4, 2, 1 by their bit[6:0]. register 130 bit[7:6] prio_2q[1:0] is used when the 2 queue conf iguration is selected, these bits are used to map the 2-bit result of ieee 802.1p from the re gisters 128, 129 or tos/diffserv mapping from registers 144-159 (for four queues) into two queues mode with priority high or low. please see the descriptions of the register 130 bits [7:6] for details. port-based priority with port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. all packets received at the priority 3 receiving port are marked as high priority and are s ent to the high-priority transmit queue if the corresponding transmit queue is split. the port registers control 0 bits [4:3 ] is used to enable port-based priority for ports 1and 2, respectively. 802.1p-based priority for 802.1p-based priority, the KSZ8864RMN examines the ingr ess (incoming) packets to determine whether they are tagged. if tagged, the 3-bit priority field in the vlan t ag is retrieved and compared against the ?priority mapping? value, as specified by the r egisters 128 and 129, both register 128/129 can map 3- bit priority field of 0-7 value to 2-bit result of 0-3 priority levels. the ?priority mapping? value is programmable. figure 6 illustrates how the 802.1p priority field is embedded in the 802.1q vlan tag.
micrel, inc. KSZ8864RMN september 2011 37 m9999-092011-1.4 figure 6. 802.1p priority field format 802.1p-based priority is enabled by bit [5] of the port registers control 0 for ports 1 and 2, respectively. the KSZ8864RMN provides the option to insert or remove the priority tagged frame's header at each individual egress port. this header, consisting of the 2 bytes vlan pr otocol id (vpid) and the 2-byte tag control information field (tci), is also referred to as the ieee 802.1q vlan tag. tag insertion is enabled by bit [2] of the port registers control 0 a nd the port register control 8 to select which source port (ingress port) pvid can be inserted on the egress port fo r ports 1, 2, 3 and 4, resp ectively. at the egress port, untagged packets are tagged with the ingr ess port?s default tag. the default tags are programmed in the port registers control 3 and control 4 for ports 1,2,3 and 4, respectively. the KSZ8864RMN will not add tags to already tagged packets. tag removal is enabled by bit [1] of the port registers control 0 for ports 1, 2, 3 and 4, respectively. at the egress port, tagged packets will have their 802.1q vlan t ags removed. the KSZ8864RMN will not modify untagged packets. the crc is recalculated for both tag insertion and tag removal. 802.1p priority field re-mapping is a qos feature that allows the KSZ8864RMN to set the ?user priority ceiling? at any ingress port by the port regi ster control 2 bit 7. if the i ngress packet?s priority field has a higher priority value than the default tag?s priority field of the i ngress port, the packet?s priority field is replaced with the default tag?s priority field. diffserv-based priority diffserv-based priority uses the tos re gisters (registers 144 to 159) in the adva nced control registers section. the tos priority control registers implement a fully decoded, 128-bit differentiated se rvices code point (dscp) register to determine packet priority from the 6-bit tos field in the ip header. when the most significant 6 bits of the tos field are fully decoded, the resultant of the 64 possibilities of dscp decoded is compared with the corresponding bits in the dscp register to determine priority. spanning tree support port 4 is the designated port for spanning tree support. the other ports (port 1 ? port 3) can be configured in one of the five spanning tree states via ?transmit enable,? ?receive enable,? and ?learning disable? register settings in registers 34, 50 for ports 1, 2 and 3, respectively. the following description shows the port setting and software ac tions taken for each of the five spanning tree states. disable state: the port should not forward or receive any packets. learning is disabled. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1." software action: the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some ent ries in the static table with ?overrid ing bit? set) and the processor should discard those packets. note: processor is connected to port 4 through mac4 sw4-mii/rmii interface. address learning is disabled on the port in this state.
micrel, inc. KSZ8864RMN september 2011 38 m9999-092011-1.4 blocking state: only packets to the proces sor are forwarded. learning is disabled. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1" software action: the processor should not send any packets to the port(s) in this state. the processor should program the ?static mac table? with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should also be set so that the switch will forward those specific packets to the processor. address learning is disabled on the port in this state. listening state: only packets to and from the pr ocessor are forwarded. learning is disabled. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1. "software action: the processor should program the static mac table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see the ?tail tagging mode? section for details. address learning is disabled on the port in this state. learning state: only packets to and from the pr ocessor are forwarded. learning is enabled. port setting: ?transmit enable = 0, re ceive enable = 0, learning disable = 0.? software action: the processor should program the static ma c table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see the ?tail tagging mode? section for details. address learning is enabled on the port in this state. forwarding state: packets are forwarded and received normally. learning is enabled. port setting: ?transmit enable = 1, re ceive enable = 1, learning disable = 0.? software action: the processor should program the static ma c table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packet s to the port(s) in this state, see ?tail tagging mode? section for details. address learning is enabled on the port in this state. rapid spanning tree support there are three operational states of the discarding, learning, and forwarding assigned to each port for rstp: discarding ports do not participate in the acti ve topology and do not learn mac addresses. discarding state: the state incl uds three states of the disabl e, blocking and listening of stp. port setting: "transmit enable = 0, re ceive enable = 0, learning disable = 1." software action: the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some ent ries in the static table with ?overrid ing bit? set) and the processor should discard those packets. when disable the por t?s learning capability (lea rning disable=?1?), set the register 1 bit5 and bit4 will flush rapidly with the port related entries in the dynamic mac table and static mac table. note: processor is connected to port 4 mac 4 sw4-mii/rm ii interface. address learning is disabled on the port in this state. ports in learning states learn mac addresse s, but do not forward user traffic. learning state: only packets to and from the pr ocessor are forwarded. learning is enabled. port setting: ?transmit enable = 0, re ceive enable = 0, learning disable = 0.? software action: the processor should program the static ma c table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packet s to the port(s) in this state, see ?tail tagging mode? section for details. address learning is enabled on the port in this state. ports in forwarding states fully participat e in both data forwarding and mac learning. forwarding state: packets are forwarded and received normally. learning is enabled.
micrel, inc. KSZ8864RMN september 2011 39 m9999-092011-1.4 port setting: ?transmit enable = 1, re ceive enable = 1, learning disable = 0.? software action: the processor should program the static ma c table with the entries that it needs to receive (e.g., bpdu packets). the ?overriding? bit should be set so that the switch will forward those specific packets to the processor. the processor may send packet s to the port(s) in this state, see ?tail tagging mode? section for details. address learning is enabled on the port in this state. rstp uses only one type of bpdu called rstp bpdus. they are similar to stp configuration bpdus with the exception of a type field set to ?version 2? for rstp and ?version 0? for stp, and a flag field carrying additional information. tail tagging mode the tail tag is only seen and used by the port 4 interf ace, which should be connect ed to a processor by mac 4 sw4-mii/rmii interface. the one byte tail tagging is used to indicate the source /destination port in port 4. only bit [3 ? 1] are used for the destination in the tail tagging byte. bi t 0 is not used. the tail t ag feature is enabled by setting register 12 bit 1. figure 7. tail tag frame format ingress to port 4 (host KSZ8864RMN) bit [3:1] destination 0,0,0 normal (address look up for destination) 0,0,1 port 1 (direct forward to port1) 0,1,0 port 2 (direct forward to port2) 1,0,0 port 3 (direct forward to port3) 1,1,1 port 1,2 and 3 (direc t forward to port 1,2,3) bit [7:4] 0,0,0,0 queue 0 is used at destination port 0,0,0,1 queue 1 is used at destination port 0,0,1,0 queue 2 is used at destination port 0,0,1,1 queue 3 is used at destination port x, 1,x,x whatever send packets to specified port in bit[3:1] 1, x,x,x bit[6:0] will be ignored egress from port 4 (KSZ8864RMN host ) bit [1:0] source 0,0 reserved 0,1 port 1 (packets from port 1) 1,0 port 2 (packets from port 2) 1,1 port 3 (packets from port 3) table 5. tail tag rules
micrel, inc. KSZ8864RMN september 2011 40 m9999-092011-1.4 igmp support there are two parts involved to support the internet group management protocol (igmp) in layer 2. the first part is igmp snooping, the second part is this igmp packet to be sent back to the subscribed port. describe them as follows. igmp snooping the KSZ8864RMN traps igmp packets and forwards them only to the pr ocessor (port 4 sw 4-mii/rmii). the igmp packets are identified as ip pa ckets (either ethernet ip packets, or ieee 802.3 snap ip packets) with ip version = 0x4 and protocol version number = 0x2. set register 5 bit [6] to ?1? to enable igmp snooping. igmp send back to the subscribed port once the host responds the received igmp packet, the ho st should knows the original igmp ingress port and send back the igmp packet to this port only, otherw ise this igmp packet will be broadcasted to all port to downgrade the performance. enable the tail tag mode, the host will know the igmp pa cket received port from tail tag bits [1:0] and can send back the response igmp packet to this subscribed port by setting the bits [3:1] in the tail tag. enable ?tail tag mode? by setting register 12 bit 1. port mirroring support KSZ8864RMN supports ?port mirror? comprehensively as: ?receive only? mirror on a port all the packets received on the port will be mirrored on the sniffer port. for example, port 1 is programmed to be ?rx sniff,? and port 2 is programmed to be the ?sniffer por t.? a packet, received on port 1, is destined to port 3 after the internal look-up. the KSZ8864RMN will forward the packet to both port 2 and port 3. KSZ8864RMN can optionally forward even ?bad? received packets to port 3. ?transmit only? mirror on a port all the packets transmitted on the port will be mirrored on t he sniffer port. for example, port 1 is programmed to be ?tx sniff,? and port 2 is programmed to be the ?sniffer port.? a packet, received on any of the ports, is destined to port 1 after the internal look-up. the ksz8864 rmn will forward the packet to both ports 1 and 2. ?receive and transmit? mirror on a port all the packets received on port a and transmitted on port b will be mirror ed on the sniffer port. to turn on the ?and? feature, set register 5 bit 0 to 1. for example, port 1 is programmed to be ?rx sniff and tx sniff,? and port 2 is programmed to be the ?sniffer port.? a packet, rece ived and transmit on port 1. the KSZ8864RMN will monitor port 1 packets on port 2. multiple ports can be selected to be ?rx sniffed? or ?tx sn iffed.? and any port can be selected to be the ?sniffer port.? all these per port features can be selected through register 17. vlan support KSZ8864RMN supports 128 active vlans and 4096 possi ble vids specified in ieee 802.1q. the KSZ8864RMN provides a 128-entry vlan table, which correspond to 4096 po ssible vids and converts to fid (7 bits) for address look-up maximum of 128 active vlans. if a non-tagged or nu ll-vid-tagged packet is received, the ingress port vid is used for look-up when 802.1q is enabled by the global register 5 control 3 bi t 7. in the vlan mode, the look-up process starts from vlan table look-u p to determine whether the vid is valid . if the vid is not valid, the packet will be dropped and its address will not be learn ed. if the vid is valid, then fid is retrieved for further look-up by the static mac table or dynamic mac tabl e. fid+da is used to determine the destination port. the followed table describles the difference actions at different situstions of da and fid+da in the stat ic mac table and dynamic mac table after the vlan table finish a look-up action. fid+sa is used for learning purposes. table 6 also describles how to learning in the dynamic mac table when vlan table has done a look-up and the static mac table without a valid entry.
micrel, inc. KSZ8864RMN september 2011 41 m9999-092011-1.4 da found in static mac table use fid flag? fid match? da+fid found in dynamic mac table action no do not care do not care no broadcast to the membership ports defined in the vlan table bit [11:7]. no do not care do not care yes send to the destination port defined in the dynamic mac table bit [57:55]. yes 0 do not care do not care send to the destination port(s) defined in the static mac table bit [52:48]. yes 1 no no broadcast to the membership ports defined in the vlan table bit [11:7]. yes 1 no yes send to the destination port defined in the dynamic mac table bit [57:55]. yes 1 yes do not care send to the destination port(s) defined in the static mac table bit [52:48]. table 6. fid+da look-up in the vlan mode sa+fid found in dynamic mac table action no the sa+fid will be learned into the dynamic table. yes time stamp will be updated. table 7. fid+sa look-up in the vlan mode advanced vlan features are also supported in ksz8864rm n, such as ?vlan ingress filtering? and ?discard non pvid? defined in bits [6:5] of the port register cont rol 2. these features can be controlled on a port basis. rate limiting support the KSZ8864RMN provides a fine resolution hardware rate lim iting. the rate step is 64kbps when the rate limit is less than 1mbps rate for 100bt or 10bt. the rate step is 1mbps when the rate limit is more than 1mbps rate for 100bt or 10bt (refer to data rate selection table which follow the end of the port register queue 0 ? 3 ingress/egress limit control section). the rate limit is independently on the ?receive side? and on the ?transmit side? on a per port basis. for 10base-t, a rate setting above 10 mbps means the rate is not lim ited. on the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control registers. on the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up egress rate control registers. the size of each frame has options to include minimum ifg (inter frame gap) or preamble byte, in addition to the data field (from packet da to fcs). ingress rate limit for ingress rate limiting, KSZ8864RMN provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames by bits [3 ? 2] of the port rate limit control register. the KSZ8864RMN counts the data rate from those selected type of frames. pack ets are dropped at the ingress port when the data rate exceeds the specified rate limit or when the flow control takes effect without packet dr opped. this occurs when the ingress rate limit flow control is enabled by the port rate limit control register bit 4. the ingress rate limiting supports the port-based, 802.1p and diffserv-based priorities , the port-based priority is fixed priority 0 ? 3 selection by bits [4 ? 3] of the port register control 0. the 802.1p and di ffserv-based priority can be mapped to priority 0 ? 3 by default of the register 128 and 129. in the ingress rate limit, set register 135 global control 19 bit3 in order for the queue-based rate limit to be enabled if use two queues or four queues mode, all related ingress ports a nd egress port should be split into two or four queues mode by the port registers co ntrol 9 and control 0. the four queues mode will use q0 ? q3 for
micrel, inc. KSZ8864RMN september 2011 42 m9999-092011-1.4 priority 0 ? 3 by bit [6-0] of the port regi ster ingress limit control 1 ? 4. the two queues mode will use q0 ? q1 for priority 0 ? 1by bit [6 ? 0] of the port register ingress limit control 1 ? 2. the priority levels in the packets of the 802.1p and diffserv can be programmed to priority 0-3 by the register 128 and 129 for a re-mapping. egress rate limit for egress rate limiting, the leaky bucket algorithm is appli ed to each output priority queue for shaping output traffic. inter frame gap is stretched on a per frame base to gener ate smooth, non-burst egress traffic. the throughput of each output priority queue is limited by t he egress rate specified by the data rate selection table followed the egress rate limit control registers. if any egress queue receives more traffic than the specifi ed egress rate throughput, packets may be accumulated in the output queue and packet memory. after the memory of t he queue or the port is used up, packet dropping or flow control will be triggered. as a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefor e slightly less than the specified egress rate. the egress rate limiting supports the port-based, 802.1p and diffserv-based prio rities, the port-based priority is fixed priority 0 ? 3 selection by bits [4 ? 3] of the port register control 0. the 802.1p and diffserv-based priority can be mapped to priority 0 ? 3 by default of the register 128 and 129. in the egress rate limit, set register 135 global control 19 bit3 for queue-based rate limit to be enabled if using two queues or four q ueues mode. all related ingress ports and egress port should be split into two or four queues mode by the port registers c ontrol 9 and control 0. the four queues mode will use q0-q3 for priority 0-3 by bit [6-0] of the port register egress limit control 1 ? 4. the two queues mode will use q0 ? q1 for priority 0 ? 1by bit [6 ? 0] of the port register egress limit control 1 ? 2. the priority levels in the packets of the 802.1p and diffserv can be programmed to priority 0 ? 3 by the register 128 and 129 for a re-mapping. with egress rate limit just use one que ue per port for the egress port rate limit , the priority packets will be based on the data rate selection table with the ra te limit exact number. if egress rate lim it use more than one queue per port for the egress port rate limit, the highest pr iority packets will be based on the data ra te selection table for the rate limit exact number and other lower priority packet rate will be limited based on 8:4:2:1 (default) priority ratio based on the highest priority rate. the transmit queue priority ratio is programmable. to reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth. transmit queue ratio programming in transmit queues 0-3 of the egress port, the default priority ratio is 8:4:2:1, the priority ratio can be programmed by the port registers control 10, 11, 12 and 13. when the transmi t rate exceed the ratio limit in the transmit queue, the transmit rate will be limited by the transmit queue 0-3 ratio of the port register control 10, 11, 12 and 13. the highest priority queue will be no limited, other lower priority queues will be limited based on the transmit queue ratio. filtering for self-address, unknown unicast/multi cast address and unknown vid packet/ip multicast enable self-address filtering, the unknown unicast packet filtering and forwarding by the register 131 global control 15. enable unknown multicast packet filtering and fo rwarding by the register 132 global control 16. enable unknown vid packet filtering and forwar ding by the register 133 global control 17. enable unknown ip multicast packet filtering and forwarding by the register 134 global control 18. this function is very useful in preventing those kind s of packets that could degr ade the quality of the port in applications such as voice over internet protocol (voi p) and the daisy chain connection to prevent packets into endless loop. configuration interface i 2 c master serial bus configuration if a 2-wire eeprom exists, the KSZ8864RMN can perform mo re advanced features like br oadcast storm protection and rate control. the eeprom should have the entire valid configuration data from re gister 0 to register 255 defined in the ?memory map,? except t he status registers and indirect regi sters. after reset, the KSZ8864RMN will start to read all control registers sequentially from the eeprom. the configuration access time (t prgm ) is less than 30ms, as shown in figure 12.
micrel, inc. KSZ8864RMN september 2011 43 m9999-092011-1.4 figure 8. KSZ8864RMN eeprom configuration timing diagram to configure the KSZ8864RMN wi th a pre-configured eeprom use the following steps: 1. at the board level, connect pi n 56 on the KSZ8864RMN to the scl pin on the eeprom. connect pin 57 on the KSZ8864RMN to the sda pin on the eeprom. 2. set the input signals ps[1:0] (pins 59 and 60, respec tively) to ?00.? this puts the KSZ8864RMN serial bus configuration into i 2 c master mode. 3. be sure the board-level reset signal is connected to the KSZ8864RMN reset signal on pin 61 (rst_n). 4. program the contents of the eeprom before placing it on the board with the desired configuration data. note that the first byte in the eeprom must be ?95? and the register1 chip id bit[7-4] = 0 for the loading to occur properly. if this value is not corr ect, all other data will be ignored. 5. place eeprom on the board and power up the board. assert t he active-low board level reset to rst_n on the KSZ8864RMN. after the reset is de-asserted, the ksz 8864rmn will begin reading configuration data from the eeprom. the configurat ion access time (t prgm ) is less than 30ms. spi slave serial bus configuration the KSZ8864RMN can also act as an spi slave device. through the spi, the entire feature set can be enabled, including ?vlan,? ?igmp snooping,? ?mib counters,? etc. the external master device can access any register from register 0 to register 127 randomly. the system should configure all the desired settings before enabling the switch in the KSZ8864RMN. to enable the switch, write a "1" to register 1 bit 0. two standard spi commands are supported (00000011 fo r ?read data,? and 00000010 for ?write data?). to speed configuration time, the KSZ8864RMN also supports multiple reads or writes. after a byte is written to or read from the KSZ8864RMN, the internal address counter automatically incremen ts if the spi slave select signal (spis_n) continues to be driven low. if spis_n is kept lo w after the first byte is read, the next byte at the next address will be shifted out on spiq. if spis_n is kept low after t he first byte is written, bits on the master out slave input (spid) line will be written to the next address. assert ing spis_n high terminates a read or write operation. this means that the spis_n signal must be asserted high and then low again before issuing another command and address. the address counter wraps back to zero once it reaches the highest address. t herefore the entire register set can be written to or read from by issuing a single command and address. the default spi clock speed is 12.5mhz. the KSZ8864RMN is able to support a spi bus up to 25mhz (set register 12 bit [5:4]=0x10). a high performance spi master is recommended to prevent internal counter overflow.
micrel, inc. KSZ8864RMN september 2011 44 m9999-092011-1.4 to use the KSZ8864RMN spi: 1. at the board level, connect KSZ8864RMN pins as follows: KSZ8864RMN pin number KSZ8864RMN signal name microprocessor signal description 58 spis_n spi slave select 56 scl spi clock 57 spid/sda master out slave input 55 spiq master in slave output table 8. spi connections 2. set the input signals ps[1:0] (pins 59 and 60, respectively) to ?10? to set th e serial configuration to spi slave mode. 3. power up the board and assert a reset signal. after reset wa it 100s, the start switch bit in register 1 will be set to ?0?. configure the desired settings in the ksz 8864rmn before setting the start register to ?1.' 4. write configuration to registers using a typical spi writ e data cycle as shown in figure 9 or spi multiple write as shown in figure 11. note that data input on spi d is registered on the rising edge of spic. 5. registers can be read and configuration can be verified wi th a typical spi read data cy cle as shown in figure 10 or a multiple read as shown in figure 12. note that read data is registered out of spiq on the falling edge of spic. 6. after configuration is written and verified, write a ?1? to register 1 bit 0 to begin KSZ8864RMN switch operation. figure 9. spi write data cycle figure 10. spi read data cycle
micrel, inc. KSZ8864RMN september 2011 45 m9999-092011-1.4 figure 11. spi multiple write figure 12. spi multiple read
micrel, inc. KSZ8864RMN september 2011 46 m9999-092011-1.4 mii management interface (miim) the KSZ8864RMN supports the standard ieee 802.3 mii management interface, also known as the management data input/output (mdio) interface. this interface allows up per-layer devices to monitor an d control the states of the KSZ8864RMN. an external device with mdc/mdio capability is used to read the phy status or configure the phy settings. further detail on the miim interface is found in clause 22.2.4.5 of the ieee 802.3u specification. the miim interface consists of the following: ? a physical connection that incorp orates the data line (pin 54 mdio) and the clock line (pin 53 mdc). ? a specific protocol that operates across the aforementioned physical co nnection that allows an external controller to communicate with the KSZ8864RMN device. ? access to a set of eight 16-bit registers, consisti ng of 8 standard miim registers [0:5h], 1d and 1f miim registers per port. the miim interface can operate up to a ma ximum clock speed of 10mhz mdc clock. table 9 depicts the mii management interface frame format. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 aaaaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 aaaaa rrrrr 10 dddddddd_dddddddd z table 9. mii management interface frame format the miim interface does not have access to all the conf iguration registers in the KSZ8864RMN. it can only access the standard miim registers. see ?miim registers?. the spi interface and mdc/mdio smi mode, on the other hand, can be used to access the entire KSZ8864RMN feature set. serial management interface (smi) the smi is the KSZ8864RMN non-standard miim interface t hat provides access to all KSZ8864RMN configuration registers. this interface allows an ex ternal device with mdc/mdio interface to completely monitor and control the states of the KSZ8864RMN. the smi interface consists of the following: a physical connection that incorporates the data line (mdio) and the clock line (mdc). a specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8864RMN device. access all KSZ8864RMN configuration r egisters. register access includes the global, port and advanced control registers 0-255 (0x00 ? 0xff), and indirect access to the st andard miim registers [0:5] and custom miim registers [29, 31]. the smi interface can operate up to a ma ximum clock speed of 10mhz mdc clock. table 10 depicts the smi frame format. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 rr11r rrrrr z0 0000_0000_dddd_dddd z write 32 1?s 01 01 rr11r rrrrr 10 xxxx_xxxx_dddd_dddd z table 10. serial management interface (smi) frame format
micrel, inc. KSZ8864RMN september 2011 47 m9999-092011-1.4 smi register read access is selected when op code is set to ?10? and bits [2:1] of the phy address is set to ?11?. the 8-bit register address is the co ncatenation of {phy address bits [4:3], phy address bits [0], reg address bit [4:0]}. ta is turn-around bits. ta bits [1:0] are ?z0? m eans the processor mdio pin is changed to input hi-z from output mode and the followed ?0? is the read response from device, as the switch confi guration registers are 8-bit wide, only the lower 8 bits of data bits [15:0] are used smi register write access is selected when op code is set to ?01? and bits [2:1] of the phy address is set to ?11?. the 8-bit register address is the co ncatenation of {phy address bits [4:3], phy address bits [0], reg address bit [4:0]}. ta bits [1:0] are set to ?10?, as the switch configurat ion registers are 8-bit wide, only the lower 8 bits of data bits [15:0] are used. to access the KSZ8864RMN registers 0-255 (0x00 ? 0xff), the following applies: phyad [4, 3, 0] and regad [4:0] are concatenated to form the 8-bit address; that is, {phyad [4,3,0], regad[4:0]} = bits [7:0] of the 8-bit address. registers are eight data bits wide. for read operation, data bi ts [15:8] are read back as 0?s. for write operation, data bits [15:8] are not defined, and hence can be set to either 0s or 1s. smi register access is the same as the miim register ac cess, except for the register access requirements presented in this section.
micrel, inc. KSZ8864RMN september 2011 48 m9999-092011-1.4 register description offset decimal hex description 0-1 0x00-0x01 chip id registers 2-13 0x02-0x0d global control registers 14-15 0x0e-0x0f power down management control registers 16-20 0x10-0x14 reserved 21-23 0x15-0x17 reserved (factory test registers) 24-31 0x18-0x1f reserved 32-36 0x20-0x24 port 1 control registers 37-39 0x25-0x27 port 1 reserved (factory test registers) 40-47 0x28-0x2f port 1 control/status registers 48-52 0x30-0x34 port 2 control registers 53-55 0x35-0x37 port 2 reserved (factory test registers) 56-63 0x38-0x3f port 2 c ontrol/status registers 64-68 0x40-0x44 reserved 69-71 0x45-0x47 reserved (factory test registers) 72-79 0x48-0x4f reserved 80-84 0x50-0x54 reserved 85-87 0x55-0x57 reserved (factory test registers) 88-95 0x58-0x5f reserved 96-103 0x60-0x67 reserved (factory testing registers) 104-109 0x68-0x6d mac address registers 110-111 0x6e-0x6f indirect access control registers 112-120 0x70-0x78 indirect data registers 121-123 0x79-0x7b reserved (factory testing registers) 124-125 0x7c-0x7d port interrupt registers 126-127 0x7e-0x7f reserved (factory testing registers) 128-135 0x80-0x87 global control registers 136 0x88 switch self test control register 137-143 0x89-0x8f qm global control registers 144-145 0x90-0x91 tos priority control registers 146-159 0x92-0x9f tos priority control registers 160-175 0xa0-0xaf reserved (factory testing registers) 176-190 0xb0-0xbe reserved 191 0xbf reserved (factory testing register)
micrel, inc. KSZ8864RMN september 2011 49 m9999-092011-1.4 offset decimal hex description 192-206 0xc0-0xce port 1 control registers 207 0xcf reserved (factory testing register) 208-222 0xd0-0xde port 2 control registers 223 0xdf reserved (factory testing register) 224-238 0xe0-0xee port 3 control registers 239 0xef reserved (factory testing register) 240-254 0xf0-0xfe port 4 control registers 255 0xff reserved (factory testing register)
micrel, inc. KSZ8864RMN september 2011 50 m9999-092011-1.4 global registers address name description mode default register 0 (0x00): chip id0 7-0 family id chip family. ro 0x95 register 1 (0x01): revision id / start switch 7-4 reserved reserved (chip id to see register 254 bit7) note: port4 rmii mode will be 0110. ro 0100 3-1 revision id revision id ro 0x0 0 start switch 1, start the chip when external pins (ps1, ps0) = (1,0) note: in (ps1,ps0) = (0,0) mode, the chip will start automatically, after trying to read the external eeprom. if eeprom does not exist, the chip will use default values for all internal registers. if eeprom is present, the contents in the eeprom will be checked. the switch will check: (1) register 0 = 0x95, (2) register 1 [7:4] = availible chip id. if this check is ok, the contents in the eeprom will override chip register default values =0, chip will not start when external pins (ps1, ps0) = (1,0) or (0,1). note: (ps1, ps0) = (1,1) fo r factory test only. 0, stop the switch function of the chip r/w 0 register 2 (0x02): global control 0 7 new back-off enable new back-off algorithm designed for unh 1 = enable 0 = disable r/w 0 6 reserved reserved. ro 0 5 flush dynamic mac table flush the entire dynamic mac table for rstp 1 = trigger the flush dynamic mac table operation. this bit is self clear 0 = normal operation note: all the entries associated with a port that has its learning capability being turned off (learning disable) will be flushed. if you want to flush the entire table, all ports learning capability must be turned off. r/w (sc) 0
micrel, inc. KSZ8864RMN september 2011 51 m9999-092011-1.4 address name description mode default 4 flush static mac table flush the matched entries in static mac table for rstp 1 = trigger the flush static mac table operation. this bit is self clear 0 = normal operation note: the matched entry is defined as the entry whose forwarding ports field contains a single port and mac address with unicast. this port, in turn, has its learning capability being turned off (learning disable). per port, multiple entries can be qualified as matched entries. r/w (sc) 0 3 reserved n/a do not change . ro 1 2 reserved n/a do not change. ro 1 1 unh mode 1, the switch will drop packets with 0x8808 in t/l filed, or da=01-80-c2-00-00-01. 0, the switch will drop pa ckets qualified as ?flow control? packets. r/w 0 0 link change age 1, link change from ?link? to ?no link? will cause fast aging (<800s) to age address table faster. after an age cycle is complete, the age logic will return to normal (300 +/- 75 seconds ). note: if any port is unplugged, all addresses will be automatically aged out. r/w 0 register 3 (0x03): global control 1 7 pass all frames 1, switch all packets including bad ones. used solely for debugging purpose. works in conjunction with sniffer mode. r/w 0 6 2k byte packet support 1 = enable support 2k byte packet 0 = disable support 2k byte packet r/w 0 5 ieee 802.3x transmit flow control disable 0, will enable transmit flow control based on an result. 1, will not enable transmit flow control regardless of an result. r/w 0 pin sm3rxd3 strap option. pd(0): enable tx flow control (default). pu(1): disable tx/rx flow control. note: sm3rxd3 has internal pull- down.
micrel, inc. KSZ8864RMN september 2011 52 m9999-092011-1.4 address name description mode default 4 ieee 802.3x receive flow control disable 0, will enable receive flow control based on an result. 1, will not enable receive flow control regardless of an result. note: bit 5 and bit 4 default values are controlled by the same pin, but they can be programmed independently. r/w 0 pin sm3rxd3 strap option. pd (0): enable rx flow control (default). pu(1): disable tx/rx flow control. note: sm3rxd3 has internal pull- down. 3 frame length field check 1, will check frame length fi eld in the ieee packets if the actual length does not match, the packet will be dropped (for l/t <1500) . r/w 0 2 aging enable 1, enable age function in the chip. 0, disable aging function. r/w 1 1 fast age enable 1 = turn on fast age (800s). r/w 0 0 aggressive back off enable 1 = enable more aggressive back-off algorithm in half duplex mode to enhance performance. this is not an ieee standard. r/w 0 pin sm3rxd0 strap option. pd(0): disable aggressive back off (default). pu(1): aggressive back off. note: sm3rxd0 has internal pull down. register 4 (0x04): global control 2 7 unicast port-vlan mismatch discard this feature is used for port vlan (described in register 17, register 33...). 1, all packets can not cross vlan boundary. 0, unicast packets (excluding unknown/ multicast/broadcast) can cross vlan boundary. r/w 1 6 multicast storm protection disable 1, ?broadcast storm protection? does not include multicast packets. only da=ffffffffffff packets will be regulated. 0, ?broadcast storm protection? includes da = ffffffffffff and da [40] = 1 packets. r/w 1 5 back pressure mode 1, carrier sense based backpressure is selected. 0, collision based backpressure is selected. r/w 1
micrel, inc. KSZ8864RMN september 2011 53 m9999-092011-1.4 address name description mode default 4 flow control and back pressure fair mode 1, fair mode is selected. in this mode, if a flow control port and a non-flow control port talk to the same destination port, packets from the non-flow control port may be dropped. this is to prevent the flow control port from being flow controlled for an extended period of time. 0, in this mode, if a flow control port and a non-flow control port talk to the sa me destination port, the flow control port will be flow controlled. this may not be ?fair? to the flow control port. r/w 1 3 no excessive collision drop 1, the switch will not drop packets when 16 or more collisions occur. 0, the switch will drop packets when 16 or more collisions occur. r/w 0 pin sm3rxd1 strap option. pd(0): (default ) drop excessive collision packets. pu(1): do not drop excessive collision packets. note: sm3rxd1 has internal pull down. 2 huge packet support 1, will accept packet sizes up to 1916 bytes (inclusive). this bit setting will override setting from bit 1 of the same register. 0, the max packet size will be determined by bit 1 of this register. r/w 0 1 legal maximum packet size check disable 1, will accept packet sizes up to 1536 bytes (inclusive). 0, 1522 bytes for tagged packets (not including packets with stpid from cpu to ports 1-4), 1518 bytes for untagged packets. any packets larger than the specified value will be dropped. r/w 0 0 reserved n/a ro 0 register 5 (0x05): global control 3 7 802.1q vlan enable 1, 802.1q vlan mode is turned on. vlan table needs to set up before the operation. 0, 802.1q vlan is disabled. r/w 0 6 igmp snoop enable on switch sw4-mii interface 1, igmp snoop enabled. all the igmp packets will be forwarded to switch mii port. 0, igmp snoop disabled. r/w 0 5 enable direct mode on switch sw4-mii interface 1, direct mode on port 4. this is a special mode for the switch mii interface. using preamble before mrxdv to direct switch to forwar d packets, bypassing internal look-up. 0, normal operation. r/w 0
micrel, inc. KSZ8864RMN september 2011 54 m9999-092011-1.4 address name description mode default 4 enable pre-tag on switch sw4-mii interface 1, packets forwarded to swit ch mii interface will be pre-tagged with the source port number (preamble before mrxdv). 0, normal operation. r/w 0 3-2 reserved n/a ro 00 1 enable ?tag? mask 1, the last 5 digits in the vid field are used as a mask to determine which port(s) the packet should be forwarded to. 0, no tag masks. note: you need to turn off the 802.1q vlan mode (reg0x5, bit 7 = 0) for this bit to work. r/w 0 0 sniff mode select 1, will do rx and tx sniff (both source port and destination port need to match). 0, will do rx or tx sniff (either source port or destination port needs to match). this is the mode used to implement rx only sniff. r/w 0 register 6 (0x06): global control 4 7 switch sw4-mii/rmii back pressure enable 1, enable half-duplex back pressure on switch mii/rmii interface. 0, disable back pressure on switch mii/rmii interface. r/w 0 6 switch sw4-mii/rmii half-duplex mode 1, enable mii/rmii interface half-duplex mode. 0, enable mii/rmii interface full-duplex mode. r/w 0 pin sm4rxd2 strap option. pd(0): (default) full-duplex mode. pu(1): half- duplex mode. note: smrxd2 has internal pull- down.
micrel, inc. KSZ8864RMN september 2011 55 m9999-092011-1.4 address name description mode default 5 switch sw4-mii/rmii flow control enable 1, enable full-duplex flow control on switch mii/rmii interface. 0, disable full-duplex flow control on switch mii/rmii interface. r/w 0 pin sm4rxd3 strap option. pd(0): (default) disable flow control. pu(1): enable flow control. note: smrxd3 has internal pull- down. 4 switch sw4-mii/rmii speed 1, the switch sw4-mii/rmii is in 10mbps mode. 0, the switch sw4-mii/rmii is in 100mbps mode r/w 0 pin sm4rxd1 strap option. pd(0): (default) enable 100mbps. pu(1): enable 10mbps. note: smrxd1 has internal pull- down. 3 null vid replacement 1, will replace null vid with port vid (12 bits). 0, no replacement for null vid. r/w 0 2-0 broadcast storm protection rate bit [10:8] this along with the next register determines how many ?64 byte blocks? of packet data allowed on an input port in a preset period. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. r/w 000 register 7 (0x07): global control 5 7-0 broadcast storm protection rate bit [7:0] this along with the previous register determines how many ?64 byte blocks? of packet data are allowed on an input port in a preset period. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. r/w 0x4a (1) register 8 (0x08): global control 6 7-0 factory testing n/a do not change. ro 0x00 register 9 (0x09): global control 7 7-0 factory testing n/a do not change. ro 0x4c note: 1. 148,800 frames/sec 50ms/interval 1% = 74 frames/interval (approx.) = 0x4a.
micrel, inc. KSZ8864RMN september 2011 56 m9999-092011-1.4 address name description mode default register 10 (0x0a): global control 8 7-0 factory testing n/ a do not change ro 0x00 register 11 (0x0b): global control 9 7 port 3 sw3-rmii reference clock edge select select the data sampling edge of switch mac3 sw3- rmii reference clock: 1 = data sampling on negative edge of refclk 0 = data sampling on positive edge of refclk (default) r/w 0 6 port 4 sw4- rmii reference clock edge select select the data sampling edge of switch mac4 sw4- rmii reference clock: 1 = data sampling on negative edge of refclk 0 = data sampling on positive edge of refclk (default) r/w 0 5 reserved n/a do not change. ro 0 4 reserved n/a do not change. ro 0 3 phy power save 1 = disable phy power save mode. 0 = enable phy power save mode. r/w 0 2 reserved n/a do not change. ro 0 0 = led mode 0. 1 = led mode 1. mode 0 mode 1 pxled1 lnk/act 100lnk/act 1 led mode pxled0 speed fullduplex r/w 0 pin sm4rxd0 - strap option. pull- down(0): enabled led mode 0. pull- up(1): enabled led mode 1. note: sm4rxd0 has internal pull- down 0. 0 spi/smi read sampling clock edge select select the spi/smi clock edge for sampling spi/smi read data 1 = trigger by rising edge of spi/smi clock (for high speed spi about 25mhz and smi about 10mhz) 0 = trigger by falling edge of spi/smi clock r/w 0
micrel, inc. KSZ8864RMN september 2011 57 m9999-092011-1.4 address name description mode default register 12 (0x0c): global control 10 7 reserved reserved ro 0 6 satus of device with rmii interface at clock mode or normal mode, default is clock mode with 25mhz crystal clock from pins x1/x2 1 = the device is in clock mode when use rmii interface, 25 mhz crystal clock input as clock source for internal pll. this internal pll will provide the 50 mhz output on the pin smrxc for rmii reference clock (default). 0 = the device is in normal mode when use sw4-rmii interface and 50 mhz clock input from external clock through pin sm4txc as device?s clock source and internal pll clock source from this pin not from the 25mhz crystal. note: this bit is set by strap onption only. write to this bit has no effect on mode selection note: the normal mode is used in sw4-rmii interface reference clock from external. ro 1 pin p1led1 strap option. pd(0): select device at normal mode when use sw4-rmii and accept 50mhz clock from external. pu(1): (default) the device is at clock mode, provide 50mhz clock in rmii. note: p1led1 has internal pull- up. 5 - 4 cpu interface clock select select the internal clock s peed for spi, mdi interface: 00 = 41.67mhz (spi up to 6.25mhz, mdc up to 6mhz) 01 = 83.33mhz default (spi scl up to 12.5mhz, mdc up to 12mhz) 10 = 125mhz (for hign speed spi about 25mhz) 11 = reserved r/w 01 3 reserved n/a do not change. ro 00 2 reserved n/a do not change. ro 1 1 tail tag enable tail tag feature is applied for port 4 only. 1 = insert 1 byte of data right before fcs 0 = do not insert r/w 0 0 pass flow control packet 1 = switch will not filter 802. 1x ?flow control? packets 0 = switch will filter 802.1x ?flow control? packets r/w 0 register 13 (0x0d): global control 11 7 - 0 factory testing n/a do not change. ro 00000000 register 14 (0x0e): power down management control 1 7 reserved n/a do not change. ro 0 6 reserved n/a do not change. ro 0
micrel, inc. KSZ8864RMN september 2011 58 m9999-092011-1.4 address name description mode default 5 pll power down pll power down enable: 1 = disable 0 = enable pll power down takes effect in energy detect mode r/w 0 4 - 3 power management mode power management mode: 00 = normal mode (d0) 01 = energy detection mode (d2) 10 = soft power down mode (d3) 11 = power saving mode (d1) r/w 00 2-0 reserved n/a do not change. ro 000 register 15 (0x0f): power down management control 2 7 - 0 go_sleep_time[7:0] when the energy detect mode is on, this value is used to control the minimum period that the no energy event has to be detected consecutively before the device enters the low power state. the unit is 20 ms. the default of go_sleep time is 1.6 seconds (80dec x 20ms). r/w 01010000
micrel, inc. KSZ8864RMN september 2011 59 m9999-092011-1.4 port registers the following registers are used to enable features that are assigned on a per port basis. the register bit assignments are the same for all ports, but the addres s for each port is different, as indicated. register 16 (0x10): reserved register 32 (0x20): port 1 control 0 register 48 (0x30): port 2 control 0 register 64 (0x40): port 3 control 0 register 80 (0x50): port 4 control 0 address name description mode default 7 broadcast storm protection enable 1, enable broadcast storm protection for ingress packets on the port. 0, disable broadcast storm protection. r/w 0 6 diffserv priority classification enable 1, enable diffserv priority classification for ingress packets on port. 0, disable diffserv function. r/w 0 5 802.1p priority classification enable 1, enable 802.1p priority classification for ingress packets on port. 0, disable 802.1p. r/w 0 4 - 3 port-based priority classification enable = 00, ingress packets on port will be classified as priority 0 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. = 01, ingress packets on port will be classified as priority 1 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. = 10, ingress packets on port will be classified as priority 2 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. = 11, ingress packets on port will be classified as priority 3 queue if ?diffserv? or ?802.1p? classification is not enabled or fails to classify. note: ?diffserv?, ?802.1p? and port priority can be enabled at the same time. the or?ed result of 802.1p and dscp overwrites the port priority. r/w 00 2 tag insertion 1, when packets are output on the port, the switch will add 802.1q tags to packets without 802.1q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress port?s ?port vid.? 0, disable tag insertion. r/w 0 1 tag removal 1, when packets are output on the port, the switch will remove 802.1q tags from packets with 802.1q tags when received. the switch will not modify packets received without tags. 0, disable tag removal. r/w 0
micrel, inc. KSZ8864RMN september 2011 60 m9999-092011-1.4 address name description mode default 0 two queues split enable this bit0 in the regist er16/32/48/64/80 should be combination with register177/193/209/225/241 bit 1 for port 1-5 will select the split of 1/2/4 queues: for port 1, [register177 bit 1, register16 bit 0] = [11], reserved [10], the port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode. [01], the port output queue is split into two priority queues or if map 802.1p to priority 0-3 mode. [00], single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority. r/w 0 register 17 (0x11): reserved register 33 (0x21): port 1 control 1 register 49 (0x31): port 2 control 1 register 65 (0x41): port 3 control 1 register 81 (0x51): port 4 control 1 address name description mode default 7 sniffer port 1, port is designated as sniffer port and will transmit packets that are monitored. 0, port is a normal port. r/w 0 6 receive sniff 1, all the packets received on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port.? 0, no receive monitoring. r/w 0 5 transmit sniff 1, all the packets transmitt ed on the port will be marked as ?monitored packets? and forwarded to the designated ?sniffer port.? 0, no transmit monitoring. r/w 0 4-0 port vlan membership define the port?s port vlan membership. bit 4 stands for port 4, bit 3 for port 3...bit 1 for port 1, bit 0 is reserved. the port can only communicate within the membership. a ?1? includes a port in the membership, a ?0? excludes a port from membership. r/w 0x1f
micrel, inc. KSZ8864RMN september 2011 61 m9999-092011-1.4 register 18 (0x12): reserved register 34 (0x22): port 1 control 2 register 50 (0x32): port 2 control 2 register 66 (0x42): port 3 control 2 register 82 (0x52): port 4 control 2 address name description mode default 7 user priority ceiling 1, if packet ?s ?user priority field? is greater than the ?user priority field? in the port default tag register, replace the packet?s ?user priority field? with the ?user priority field? in the port def ault tag register control 3. 0, no replace packet?s priority filed with port default tag priority filed of the port register control 3 bit [7:5]. r/w 0 6 ingress vlan filtering. 1, the switch will discard packates whose vid port membership in vlan table bit[20:16] does not include the ingress port. 0, no ingress vlan filtering. r/w 0 5 discard non-pvid packets 1, the switch will discard packets whose vid does not match ingress port default vid. 0, no packets will be discarded. r/w 0 4 force flow control 1, will always enable rx and tx flow control on the port, regardless of an result. 0, the flow control is enabled based on an result (default) r/w 0 3 back pressure enable 1, enable port half-duplex back pressure. 0, disable port half-duplex back pressure. r/w 0 pin sm3rxd2 strap option. pull-down (0): disable back pressure. pull-up(1): enable back pressure. note: sm3rxd2 has internal pull- down. 2 transmit enable 1, enable packet transmission on the port. 0, disable packet transmission on the port. r/w 1 1 receive enable 1, enable packet reception on the port. 0, disable packet reception on the port. r/w 1 0 learning disable 1, disable switch address learning capability. 0, enable switch address learning. r/w 0 note: bits 2-0 are used for spanning tree s upport. see ?spanning tree support? section.
micrel, inc. KSZ8864RMN september 2011 62 m9999-092011-1.4 register 19 (0x13): reserved register 35 (0x23): port 1 control 3 register 51 (0x33): port 2 control 3 register 67 (0x43): port 3 control 3 register 83 (0x53): port 4 control 3 address name description mode default 7-0 default tag [15:8] port?s default tag, containing: 7-5: user priority bits 4: cfi bit 3-0 : vid[11:8] r/w 0 register 20 (0x14): reserved register 36 (0x24): port 1 control 4 register 52 (0x34): port 2 control 4 register 68 (0x44): port 3 control 4 register 84 (0x54): port 4 control 4 address name description mode default 7-0 default tag [7:0] default port 1?s tag, containing: 7-0: vid[7:0] r/w 1 note: registers 35 and 36 (and those corresponding to other ports) se rve two purposes: (1) associated with the ingress untagged packe ts, and used for egress tagging; (2) default vid for the ingress untagged or null-vid-tagged packets, and used for address look up.
micrel, inc. KSZ8864RMN september 2011 63 m9999-092011-1.4 register 87 (0x57): rmii management control register address name description mode default 7 - 4 reserved ro 0000 3 port 4 mac4 sw4-rmii 50mhz clock output disable disable the output of por t 4 sw4-rmii 50 mhz output clock on rxc pin when 50mhz clock is not being used by the device and the 50mhz clock from external oscillator or opposite device in rmii mode 1 = disable clock output when rxc pin is not used in rmii mode 0 = enable clock output in rmii mode r/w 0 2 - 0 reserved n/a do not change ro 000 register 25 (0x19): reserved register 41 (0x29): port 1 status 0 register 57 (0x39): port 2 status 0 register 73 (0x49): port 3 status 0 for spd/dpx register 89 (0x59): port 4 status 0 for spd/dpx address name description mode default 7 hp_mdix 1 = hp auto mdi/mdi-x mode 0 = micrel auto mdi/mdi-x mode r/w 1 6 reserved n/a do not change ro 0 5 polrvs 1 = polarity is reversed 0 = polarity is not reversed ro 0 4 transmit flow control enable 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive ro 0 3 receive flow control enable 1 = receive flow control feature is active 0 = receive flow control feature is inactive ro 0 2 operation speed 1 = link speed is 100mbps 0 = link speed is 10mbps ro 0 1 operation duplex 1 = link duplex is full 0 = link duplex is half ro 0 0 reserved n/a do not change ro 0
micrel, inc. KSZ8864RMN september 2011 64 m9999-092011-1.4 register 26 (0x1a): reserved register 42 (0x2a): port 1 phy special control/status register 58 (0x3a): port 2 phy special control/status register 74 (0x4a): reserved register 90 (0x5a): reserved address name description mode default 7-4 reserved n/a do not change ro 0000 3 force_lnk 1 = force link pass 0 = normal operation r/w 0 2 pwrsave 1 = enable power saving 0 = disable power saving r/w 0 1 remote loopback 1 = perform remote loopback, loopback on port 1 as follows: port 1 (reg. 26, bit 1 = ?1?) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 1?s phy end: txp1/txm1 (port 1) setting reg. 42, 58, 74, 90, bit 1 = ?1? will perform remote loopback on port 2, 3, 4, 5. 0 = normal operation. r/w 0 0 reserved n/a do not change ro 0 register 27 (0x1b): reserved register 43 (0x2b): reserved register 59 (0x3b): reserved register 75 (0x4b): reserved register 91 (0x5b): reserved address name description mode default 7-0 reserved n/a do not change ro 0x00
micrel, inc. KSZ8864RMN september 2011 65 m9999-092011-1.4 register 28 (0x1c): reserved register 44 (0x2c): port 1 control 5 register 60 (0x3c): port 2 control 5 register 76 (0x4c): reserved register 92 (0x5c): reserved address name description mode default 7 disable auto-negotiation 1, disable auto-negotiation, speed and duplex are decided by bit 6 and 5 of the same register. 0, auto-negotiation is on. r/w 0 6 forced speed 1, forced 100bt if an is disabled (bit 7). 0, forced 10bt if an is disabled (bit 7). r/w 1 5 forced duplex 1, forced full-duplex if (1) an is disabled or (2) an is enabled but failed. 0, forced half-duplex if (1) an is disabled or (2) an is enabled but failed (default). r/w 0 4 advertised flow control capability 1, advertise flow control capability. 0, suppress flow control capability from transmission to link partner. r/w 1 3 advertised 100bt full- duplex capability 1, advertise 100bt full-duplex capability. 0, suppress 100bt full-duplex capability from transmission to link partner. r/w 1 2 advertised 100bt half- duplex capability 1, advertise 100bt half-duplex capability. 0, suppress 100bt half-duplex capability from transmission to link partner. r/w 1 1 advertised 10bt full- duplex capability 1, advertise 10bt full-duplex capability. 0, suppress 10bt full-duplex capability from transmission to link partner. r/w 1 0 advertised 10bt half- duplex capability 1, advertise 10bt half-duplex capability. 0, suppress 10bt half-duplex capability from transmission to link partner. r/w 1
micrel, inc. KSZ8864RMN september 2011 66 m9999-092011-1.4 register 29 (0x1d): reserved register 45 (0x2d): port 1 control 6 register 61 (0x3d): port 2 control 6 register 77 (0x4d): port 3 control 6 for mac loop-back register 93 (0x5d): port 4 control 6 for mac loop-back address name description mode default 7 led off 1, turn off all port?s leds (pxled0, pxled1, where ?x? is the port number). these pins will be driven high if this bit is set to one. 0, normal operation. r/w 0 6 txids 1, disable port?s transmitter. 0, normal operation. r/w 0 5 restart an 1, restart auto-negotiation. 0, normal operation. r/w (sc) 0 4 reserved n/a ro 0 3 power down 1, power down. 0, normal operation. r/w 0 2 disable auto mdi/mdi-x 1, disable auto mdi/mdi-x function. 0, enable auto mdi/mdi-x function. r/w 0 1 forced mdi 1, if auto mdi/mdi-x is dis abled, force phy into mdix mode. 0, mdi mode. r/w 0 0 mac loopback 1 = perform mac loopback, loop back path as follows: e.g. set port 1 mac loopback (reg. 45, bit 0 = ?1?), use port 2 as monitor port. the packets will transfer start: port 2 receiving (also can start to receive packets from port 1). loop-back: port 1?s mac. end: port 2 transmitting (also can end at port 1). setting reg. 77, 93, bit 0 = ?1? will perform mac loopback on port 3, 4 respectively with monitor port 2. 0 = normal operation. r/w 0 note: from bit [7-1] are reserved for the port 3 and port 4.
micrel, inc. KSZ8864RMN september 2011 67 m9999-092011-1.4 register 30 (0x1e): reserved register 46 (0x2e): port 1 status 1 register 62 (0x3e): port 2 status 1 register 78 (0x4e): reserved register 94 (0x5e): reserved address name description mode default 7 mdix status 1, mdi-x. 0, mdi. ro 0 6 an done 1, an done. 0, an not done. ro 0 5 link good 1, link good. 0, link not good. ro 0 4 partner flow control capability 1, link partner flow control capable. 0, link partner not flow control capable. ro 0 3 partner 100bt full- duplex capability 1, link partner 100bt full-duplex capable. 0, link partner not 100bt full-duplex capable. ro 0 2 partner 100bt half- duplex capability 1, link partner 100bt half-duplex capable. 0, link partner not 100bt half-duplex capable. ro 0 1 partner 10bt full-duplex capability 1, link partner 10bt full-duplex capable. 0, link partner not 10bt full-duplex capable. ro 0 0 partner 10bt half-duplex capability 1, link partner 10bt half-duplex capable. 0, link partner not 10bt half-duplex capable. ro 0 register 31 (0x1f): reserved register 47 (0x2f): port 1 control 7 and status 2 register 63 (0x3f): port 2 control 7 and status 2 register 79 (0x4f): reserved register 95 (0x5f): reserved address name description mode default 7 phy loopback 1 = perform phy loopback, loop back path as follows: e.g. set port 1 phy loopback (reg. 47, bit 7 = ?1?) use the port 2 as monitor port. the packets will transfer start: port 2 receiving (also can start from port 1). loopback: pmd/pma of port 1?s phy end: port 2 transmitting (also can end at port 1). setting reg. 63 bit 7 = ?1? will perform phy loopback on port 2 with monitor port 1. 0 = normal operation. r/w 0 6 reserved n/a do not change ro 0
micrel, inc. KSZ8864RMN september 2011 68 m9999-092011-1.4 address name description mode default 5 phy isolate 1, electrical isolation of phy from mii and tx+/tx-. 0, normal operation. r/w 0 4 soft reset 1, phy soft reset. this bit is self clear. 0, normal operation. r/w (sc) 0 3 force link 1, force link in the phy. 0, normal operation r/w 0 2-0 port operation mode indication indicate the current stat e of port operation mode: [000] = reseved [001] = still in auto-negotiation [010] = 10base-t half duplex [011] = 100base-tx half duplex [100] = reserved [101] = 10base-t full duplex [110] = 100base-tx full duplex [111] = reserved ro 001 note: port control 12 and 13, 14 and port status 1,2 contents can be a ccessed by miim (mdc/mdio) interface via the standard miim regi ster definition.
micrel, inc. KSZ8864RMN september 2011 69 m9999-092011-1.4 advanced control registers registers 104 to 109 define the switching engine?s mac address. th is 48-bit address is used as t he source address in mac pause control frames, or is used for self mac address filtering, see the register 134 also. address name description mode default register 104 (0x68): mac address register 0 7-0 maca[47:40] r/w 0x00 register 105 (0x69): mac address register 1 7-0 maca[39:32] r/w 0x10 register 106 (0x6a): mac address register 2 7-0 maca[31:24] r/w 0xa1 register 107 (0x6b): mac address register 3 7-0 maca[23:16] r/w 0xff register 108 (0x6c): mac address register 4 7-0 maca[15:8] r/w 0xff register 109 (0x6d): mac address register 5 7-0 maca[7:0] r/w 0xff use registers 110 and 111 to read or write data to the static ma c address table, vlan table, dynamic address table, or the mib counters. address name description mode default register 110 (0x6e): indirect access control 0 7-5 reserved reserved. r/w 000 4 read high write low 1, read cycle. 0, write cycle. r/w 0 3-2 table select 00 = static mac address table selected. 01 = vlan table selected. 10 = dynamic address table selected. 11 = mib counter selected. r/w 0 1-0 indirect address high bit 9-8 of indirect address. r/w 00 register 111 (0x6f): indirect access control 1 7-0 indirect address low bit 7- 0 of indirect address. r/w 00000000 note: write to register 111 will actually trigger a command. read or write access will be decided by bit 4 of register 110. address name description mode default register 112 (0x70): indirect data register 8 68-64 indirect data bit 68- 64 of indirect data. r/w 00000 register 113 (0x71): indirect data register 7 63-56 indirect data bit 63-56 of indirect data. r/w 00000000 register 114 (0x72): indirect data register 6 55-48 indirect data bit 55-48 of indirect data. r/w 00000000
micrel, inc. KSZ8864RMN september 2011 70 m9999-092011-1.4 address name description mode default register 115 (0x73): indirect data register 5 47-40 indirect data bit 47-40 of indirect data. r/w 00000000 register 116 (0x74): indirect data register 4 39-32 indirect data bit 39-32 of indirect data. r/w 00000000 register 117 (0x75): indirect data register 3 31-24 indirect data bit of 31- 24 of indirect data r/w 00000000 register 118 (0x76): indirect data register 2 23-16 indirect data bit 23-16 of indirect data. r/w 00000000 register 119 (0x77): indirect data register 1 15-8 indirect data bit 15-8 of indirect data. r/w 00000000 register 120 (0x78): indirect data register 0 7-0 indirect data bit 7-0 of indirect data. r/w 00000000 register 124 (0x7c): interrupt status register 7 - 3 reserved reserved. ro 000 2 port 2 interrupt status 1, port 2 interrupt request 0, normal note: this bit is set by port 2 link change. write a ?1? to clear this bit ro 0 1 port 1 interrupt status 1, port 1 interrupt request 0, normal note: this bit is set by port 1 link change. write a ?1? to clear this bit ro 0 0 reserved reserved. ro 0 register 125 (0x7d): interrupt mask register 7 - 3 reserved reserved. ro 000 2 port 2 interrupt mask 1, port 2 interrupt mask 0, normal r/w 0 1 port 1 interrupt mask 1, port 1 interrupt mask 0, normal r/w 0 0 reserved reserved. ro 0
micrel, inc. KSZ8864RMN september 2011 71 m9999-092011-1.4 the registers 128, 129 can be used to map from 802.1p priority field 0-7 to switch?s four priority queues 0-3, 0x3 is highest p riority queues as priority 3, 0x0 is lowest priority queues as priority 0. address name description mode default register 128 (0x80): global control 12 7 - 6 tag_0x3 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x3. r/w 0x1 5 - 4 tag_0x2 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x2. r/w 0x1 3 - 2 tag_0x1 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x1. r/w 0x0 1 - 0 tag_0x0 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x0. r/w 0x0 register 129 (0x81): global control 13 7 - 6 tag_0x7 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x7. r/w 0x3 5 - 4 tag_0x6 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x6. r/w 0x3 3 - 2 tag_0x5 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x5. r/w 0x2 1 - 0 tag_0x4 ieee 802.1p mapping. the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x4. r/w 0x2 register 130 (0x82): global control 14 7 - 6 pri_2q[1:0] (note that program prio_2q[1:0] = 01 is not supported and should be avoided) when the 2 queue configurat ion is selected, these pri_2q[1:0] bits are used to map the 2-bit result of ieee 802.1p from register 128/129 or tos/diffserv from register 144- 159 m apping (for 4 queues) into two queues low/high priorities. 2-bit result of ieee 802.1p or tos/diffserv 00 (0) = map to low priority queue 01 (1) = prio_2q[0] map to low/high priority queue 10 (2) = prio_2q[1] map to low/high priority queue 11 (3) = map to high priority queue pri_2q[1:0] = 00: result 0,1,2 are low priority. 3 is high priority. 10: result 0,1 are low priority. 2,3 are high priority (default). 11: result 0 is low priority. 1,2,3 are high priority. r/w 10 5 reserved n/a do not change. ro 0
micrel, inc. KSZ8864RMN september 2011 72 m9999-092011-1.4 address name description mode default 4 reserved n/a do not change. ro 0 3 - 2 reserved n/a do not change. ro 01 1 reserved n/a do not change. ro 0 0 reserved n/a do not change. ro 0 . register 131 (0x83): global control 15 7 reserved n/a ro 0 6 reserved n/a ro 0 5 unknown unicast packet forward 1 = enable supporting unknown unicast packet forward 0 = disable r/w 0 4 - 0 unknown unicast packet forward port map 00000 = filter uknown unicast packet 00001 = forward uknown unicast packet to port 1 00011 = forward uknown unicast packet to port 1, port 2 11111 = broadcast uknown unicast packet to all ports r/w 00000 register 132 (0x84): global control 16 7 - 6 chip i/o output drive strength select[1:0] output drive strength select[1:0] = 00 = 4ma drive strength 01 = 8ma drive strength (default) 10 = 12ma drive strength 11 = 16 ma drive strength r/w 01 5 unknown multicast packet forward (not including ip multicast packet) 1 = enable supporting unknown multicast packet forward 0 = disable r/w 0 4 - 0 unknown multicast packet forward port map 00000 = filter uknown multiicast packet 00001 = forward uknown multicast packet to port 1 00011 = forward uknown multicast packet to port 1, port 2 11111 = broadcast uknown multicast packet to all ports r/w 00000 register 133(0x85): global control 17 7 - 6 reserved ro 00 5 unknown vid packet forward 1 = enable supporting unknown vid packet forward 0 = disable r/w 0 4 - 0 unknown vid packet forward port map 00000 = filter uknown vid packet 00001 = forward uknown vid packet to port 1 00011 = forward uknown vid packet to port 1, port 2 11111 = broadcast uknown vid packet to all ports r/w 00000
micrel, inc. KSZ8864RMN september 2011 73 m9999-092011-1.4 address name description mode default register 134 (0x86): global control 18 7 reserved n/a ro 0 6 self address filter enable 1 = enable filtering of self-address unicast and multicast packet 0 = do not filter self-address packet note: the self-address filter ing will filter packets on the egress port , self mac address is assigned in the register 104-109. r/w 0 5 unknown ip multicast packet forward 1 = enable supporting unknown ip multicast packet forward 0 = disable r/w 0 4 - 0 unknown ip multicast packet forward port map 00000 = filter uknown ip multiicast packet 00001 = forward uknown ip multicast packet to port 1 00011 = forward uknown ip multicast packet to port 1, port 2 11111 = broadcast uknown ip multicast packet to all ports r/w 00000 register 135 (0x87): global control 19 7 reserved n/a do not change. ro 0 6 reserved n/a do not change. ro 0 5 - 4 ingress rate limit period the unit per iod for calculating ingress rate limit 00 = 16 ms 01 = 64 ms 1x = 256 ms r/w 01 3 queue-based egress rate limit enabled enable queue-based egress rate limit 0 = port-base egress rate limit (default) 1 = queue-based egress rate limit r/w 0 2 insertion source port pvid tag selection enable 1 = enable source port pvid tag insertion or non- insertion option on the egress port for each source port pvid based on the port s registers control 8. 0 = disable, all packets from any ingress port will be inserted pvid based on port register control 0 bit 2. r/w 0 1 - 0 reserved n/a do not change. ro 00 register 144 (0x90): tos priority control register 0 the ipv4/ipv6 tos priority control regist ers implement a fully decoded 64 bit different iated services code point (dscp) registe r used to determine priority from the 6 bit tos field in the ip header. t he most significant 6 bits of the tos field are fully decoded in to 64 possibilities, and the singul ar code that results is mapped to the value in the corresponding bit in the dscp register. 7 - 6 dscp[7:6] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffserv/traffic class value is 0x03. r/w 00
micrel, inc. KSZ8864RMN september 2011 74 m9999-092011-1.4 address name description mode default 5 - 4 dscp[5:4] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffserv/traffic class value is 0x02 r/w 00 3 - 2 dscp[3:2] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffserv/traffic class value is 0x01 r/w 00 1 - 0 dscp[1:0] ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when bits[7:2] of the frame?s ip tos/diffserv/traffic class value is 0x00 r/w 00 register 145 (0x91): tos priority control register 1 7 - 6 dscp[15:14] ipv4 and ipv6 mapping _ for value 0x07 r/w 00 5 - 4 dscp[13:12] ipv4 and ipv6 mapping _ for value 0x06 r/w 00 3 - 2 dscp[11:10] ipv4 and ipv6 mapping _ for value 0x05 r/w 00 1 - 0 dscp[9:8] ipv4 and ipv6 mapping _ for value 0x04 r/w 00 register 146 (0x92): tos priority control register 2 7 - 6 dscp[23:22] ipv4 and ipv6 mapping _ for value 0x0b r/w 00 5 - 4 dscp[21:20] ipv4 and ipv6 mapping _ for value 0x0a r/w 00 3 - 2 dscp[19:18] ipv4 and ipv6 mapping _ for value 0x09 r/w 00 1 - 0 dscp[17:16] ipv4 and ipv6 mapping _ for value 0x08 r/w 00 register 147 (0x93): tos priority control register 3 7 - 6 dscp[31:30] ipv4 and ipv6 mapping _ for value 0x0f r/w 00 5 - 4 dscp[29:28] ipv4 and ipv6 mapping _ for value 0x0e r/w 00 3 - 2 dscp[27:26] ipv4 and ipv6 mapping _ for value 0x0d r/w 00 1 - 0 dscp[25:24] ipv4 and ipv6 mapping _ for value 0x0c r/w 00 register 148 (0x94): tos priority control register 4 7 - 6 dscp[39:38] ipv4 and ipv6 mapping _ for value 0x13 r/w 00 5 - 4 dscp[37:36] ipv4 and ipv6 mapping _ for value 0x12 r/w 00 3 - 2 dscp[35:34] ipv4 and ipv6 mapping _ for value 0x11 r/w 00 1 - 0 dscp[33:32] ipv4 and ipv6 mapping _ for value 0x10 r/w 00 register 149 (0x95): tos priority control register 5 7 - 6 dscp[47:46] ipv4 and ipv6 mapping _ for value 0x17 r/w 00 5 - 4 dscp[45:44] ipv4 and ipv6 mapping _ for value 0x16 r/w 00 3 - 2 dscp[43:42] ipv4 and ipv6 mapping _ for value 0x15 r/w 00 1 - 0 dscp[41:40] ipv4 and ipv6 mapping _ for value 0x14 r/w 00
micrel, inc. KSZ8864RMN september 2011 75 m9999-092011-1.4 address name description mode default register 150 (0x96): tos priority control register 6 7 - 6 dscp[55:54] ipv4 and ipv6 mapping _ for value 0x1b r/w 00 5 - 4 dscp[53:52] ipv4 and ipv6 mapping _ for value 0x1a r/w 00 3 - 2 dscp[51:50] ipv4 and ipv6 mapping _ for value 0x19 r/w 00 1 - 0 dscp[49:48] ipv4 and ipv6 mapping _ for value 0x18 r/w 00 register 151 (0x97): tos priority control register 7 7 - 6 dscp[63:62] ipv4 and ipv6 mapping _ for value 0x1f r/w 00 5 - 4 dscp[61:60] ipv4 and ipv6 mapping _ for value 0x1e r/w 00 3 - 2 dscp[59:58] ipv4 and ipv6 mapping _ for value 0x1d r/w 00 1 - 0 dscp[57:56] ipv4 and ipv6 mapping _ for value 0x1c r/w 00 register 152 (0x98): tos priority control register 8 7 - 6 dscp[71:70] ipv4 and ipv6 mapping _ for value 0x23 r/w 00 5 - 4 dscp[69:68] ipv4 and ipv6 mapping _ for value 0x22 r/w 00 3 - 2 dscp[67:66] ipv4 and ipv6 mapping _ for value 0x21 r/w 00 1 - 0 dscp[65:64] ipv4 and ipv6 mapping _ for value 0x20 r/w 00 register 153 (0x99): tos priority control register 9 7 - 6 dscp[79:78] ipv4 and ipv6 mapping _ for value 0x27 r/w 00 5 - 4 dscp[77:76] ipv4 and ipv6 mapping _ for value 0x26 r/w 00 3 - 2 dscp[75:74] ipv4 and ipv6 mapping _ for value 0x25 r/w 00 1 - 0 dscp[73:72] ipv4 and ipv6 mapping _ for value 0x24 r/w 00 register 154 (0x9a): tos priority control register 10 7 - 6 dscp[87:86] ipv4 and ipv6 mapping _ for value 0x2b r/w 00 5 - 4 dscp[85:84] ipv4 and ipv6 mapping _ for value 0x2a r/w 00 3 - 2 dscp[83:82] ipv4 and ipv6 mapping _ for value 0x29 r/w 00 1 - 0 dscp[81:80] ipv4 and ipv6 mapping _ for value 0x28 r/w 00 register 155 (0x9b): tos priority control register 11 7 - 6 dscp[95:94] ipv4 and ipv6 mapping _ for value 0x2f r/w 00 5 - 4 dscp[93:92] ipv4 and ipv6 mapping _ for value 0x2e r/w 00 3 - 2 dscp[91:90] ipv4 and ipv6 mapping _ for value 0x2d r/w 00 1 - 0 dscp[89:88] ipv4 and ipv6 mapping _ for value 0x2c r/w 00 register 156 (0x9c): tos priority control register 12 7 - 6 dscp[103:102] ipv4 and ipv6 mapping _ for value 0x33 r/w 00 5 - 4 dscp[101:100] ipv4 and ipv6 mapping _ for value 0x32 r/w 00 3 - 2 dscp[99:98] ipv4 and ipv6 mapping _ for value 0x31 r/w 00 1 - 0 dscp[97:96] ipv4 and ipv6 mapping _ for value 0x30 r/w 00
micrel, inc. KSZ8864RMN september 2011 76 m9999-092011-1.4 address name description mode default register 157 (0x9d): tos priority control register 13 7 - 6 dscp[111:110] ipv4 and ipv6 mapping _ for value 0x37 r/w 00 5 - 4 dscp[109:108] ipv4 and ipv6 mapping _ for value 0x36 r/w 00 3 - 2 dscp[107:106] ipv4 and ipv6 mapping _ for value 0x35 r/w 00 1 - 0 dscp[105:104] ipv4 and ipv6 mapping _ for value 0x34 r/w 00 register 158 (0x9e): tos priority control register 14 7 - 6 dscp[119:118] ipv4 and ipv6 mapping _ for value 0x3b r/w 00 5 - 4 dscp[117:116] ipv4 and ipv6 mapping _ for value 0x3a r/w 00 3 - 2 dscp[115:114] ipv4 and ipv6 mapping _ for value 0x39 r/w 00 1 - 0 dscp[113:112] ipv4 and ipv6 mapping _ for value 0x38 r/w 00 register 159 (0x9f): tos priority control register 15 7 - 6 dscp[127:126] ipv4 and ipv6 mapping _ for value 0x3f r/w 00 5 - 4 dscp[125:124] ipv4 and ipv6 mapping _ for value 0x3e r/w 00 3 - 2 dscp[123:122] ipv4 and ipv6 mapping _ for value 0x3d r/w 00 1 - 0 dscp[121:120] ipv4 and ipv6 mapping _ for value 0x3c r/w 00 register 176 (0xb0): reserved register 192 (0xc0): port 1 control 8 register 208 (0xd0): port 2 control 8 register 224 (0xe0): port 3 control 8 register 240 (0xf0): port 4 control 8 7 - 4 reserved ro 0000 3 insert source port pvid for untagged packet destination to highest egress port note: enabled by the register 135 bit 2 register 208: insert source port 2 pvid for untagged frame at egress port 4 register 224: insert source port 3 pvid for untagged frame at egress port 4 register 240: insert source port 4 pvid for untagged frame at egress port 3 r/w 0 2 insert source port pvid for untagged packet destination to second highest egress port note: enabled by the register 135 bit 2 register 192: insert source port 1 pvid for untagged frame at egress port 3 register 208: insert source port 2 pvid for untagged frame at egress port 3 register 224: insert source port 3 pvid for untagged frame at egress port 2 register 240: insert source port 4 pvid for untagged frame at egress port 2. r/w 0
micrel, inc. KSZ8864RMN september 2011 77 m9999-092011-1.4 address name description mode default 1 insert source port pvid for untagged packet destination to second lowest egress port note: enabled by the register 135 bit 2 register 192: insert source port 1 pvid for untagged frame at egress port 2 register 208: insert source port 2 pvid for untagged frame at egress port 1 register 224: insert source port 3 pvid for untagged frame at egress port 1 register 240: insert source port 4 pvid for untagged frame at egress port 1 r/w 0 0 reserved reserved ro 0 register 177 (0xb1): reserved register 193 (0xc1): port 1 control 9 register 209 (0xd1): port 2 control 9 register 225 (0xe1): port 3 control 9 register 241 (0xf1): port 4 control 9 7 - 2 reserved ro 0000000 1 4 queue split enable this bit in combination with register16/32/48/64/80 bit 0 will select the split of 1/2/4 queues: {register177 bit 1, register16 bit 0}= 11, reserved. 10, the port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode. 01, the port output queue is split into two priority queues or if map 802.1p to priority 0-3 mode. 00, single output queue on the port. there is no priority differentiation even though packets are classified into high and low priority r/w 0 0 enable dropping tag 0 = disable tag drop 1 = enable tag drop r/w 0 register 178 (0xb2): reserved register 194 (0xc2): port 1 control 10 register 210 (0xd2): port 2 control 10 register 226 (0xe2): port 3 control 10 register 242 (0xf2): port 4 control 10 7 enable port transmit queue 3 ratio 0, strict priority, will transmit all the packets from this priority queue 3 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 3 within a certain time r/w 1 6 - 0 port transmit queue 3 ratio[6:0] packet number for transmit queue 3 for highest priority packets in four queues mode r/w 0001000
micrel, inc. KSZ8864RMN september 2011 78 m9999-092011-1.4 address name description mode default register 179 (0xb3): reserved register 195 (0xc3): port 1 control 11 register 211 (0xd3): port 2 control 11 register 227 (0xe3): port 3 control 11 register 243 (0xf3): port 4 control 11 7 enable port transmit queue 2 ratio 0, strict priority, will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time r/w 1 6 - 0 port transmit queue 2 ratio[6:0] packet number for transmit queue 2 for high/low priority packets in high/low priority packets in four queues mode r/w 0000100 register 180 (0xb4): reserved register 196 (0xc4): port 1 control 12 register 212 (0xd4): port 2 control 12 register 228 (0xe4): port 3 control 12 register 244 (0xf4): port 4 control 12 7 enable port transmit queue 1 rate 0, strict priority, will transmit all the packets from this priority queue 1 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time r/w 1 6 - 0 port transmit queue 1 ratio[6:0] packet number for transmit queue 1 for low/high priority packets in four queues mode and high priority packets in two queues mode r/w 0000010 register 181 (0xb5): reserved register 197 (0xc5): port 1 control 13 register 213 (0xd5): port 2 control 13 register 229 (0xe5): port 3 control 13 register 245 (0xf5): port 4 control 13 7 enable port transmit queue 0 rate 0, strict priority, will transmit all the packets from this priority queue 0 before transmit lower priority queue. 1, bit[6:0] reflect the packet number allow to transmit from this priority queue 0 within a certain time r/w 1 6 - 0 port transmit queue 0 ratio[6:0] packet number for transmit queue 0 for lowest priority packets in four queues mode and low priority packets in two queues mode r/w 0000001
micrel, inc. KSZ8864RMN september 2011 79 m9999-092011-1.4 address name description mode default register 182 (0xb6): reserved register 198 (0xc6): port 1 rate limit control register 214 (0xd6): port 2 rate limit control register 230 (0xe6): port 3 rate limit control register 246 (0xf6): port 4 rate limit control 7 - 5 reserved ro 000 4 ingress rate limit flow control enable 1 = flow control is asserted if the port?s receive rate is exceeded 0 = flow control is not asserted if the port?s receive rate is exceeded r/w 0 3 - 2 limit mode ingress limit mode these bits determine what kinds of frames are limited and counted against ingress rate limiting. = 00, limit and count all frames = 01, limit and count broadcast, multicast, and flooded unicast frames = 10, limit and count broadcast and multicast frames only = 11, limit and count broadcast frames only r/w 00 1 count ifg count ifg bytes = 1, each frame?s minimum inter frame gap (ifg) bytes (12 per frame) are included in ingress and egress rate limiting calculations. = 0, ifg bytes are not counted. r/w 0 0 count pre count preamble bytes = 1, each frame?s preamble bytes (8 per frame) are included in ingress and egress rate limiting calculations. = 0, preamble bytes are not counted. r/w 0 register 183 (0xb7): reserved register 199 (0xc7): port 1 priority 0 ingress limit control 1 register 215 (0xd7): port 2 priority 0 ingress limit control 1 register 231 (0xe7): port 3 priority 0 ingress limit control 1 register 247 (0xf7): port 4 priority 0 ingress limit control 1 7 reserved ro 0 6 - 0 port based priority 0 ingress limit ingress data rate limit for priority 0 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000
micrel, inc. KSZ8864RMN september 2011 80 m9999-092011-1.4 address name description mode default register 184 (0xb8): reserved register 200 (0xc8): port 1 priority 1 ingress limit control 2 register 216 (0xd8): port 2 priority 1 ingress limit control 2 register 232 (0xe8): port 3 priority 1 ingress limit control 2 register 248 (0xf8): port 4 priority 1 ingress limit control 2 7 reserved ro 0 6 - 0 port based priority 1 ingress limit ingress data rate limit for priority 1 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000 register 185 (0xb9): reserved register 201 (0xc9): port 1 priority 2 ingress limit control 3 register 217 (0xd9): port 2 priority 2 ingress limit control 3 register 233 (0xe9): port 3 priority 2 ingress limit control 3 register 249 (0xf9): port 4 priority 2 ingress limit control 3 7 reserved ro 0 6 - 0 port based priority 2 ingress limit ingress data rate limit for priority 2 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000 register 186 (0xba): reserved register 202 (0xca): port 1 priority 3 ingress limit control 4 register 218 (0xda): port 2 priority 3 ingress limit control 4 register 234 (0xea): port 3 priority 3 ingress limit control 4 register 250 (0xfa): port 4 priority 3 ingress limit control 4 7 reserved ro 0 6 - 0 port based priority 3 ingress limit ingress data rate limit for priority 3 frames ingress traffic from this port is shaped according to the data rate selected table. see the table follow the end of egress limit control registers r/w 0000000
micrel, inc. KSZ8864RMN september 2011 81 m9999-092011-1.4 address name description mode default register 187 (0xbb): reserved register 203 (0xcb): port 1 queue 0 egress limit control 1 register 219 (0xdb): port 2 queue 0 egress limit control 1 register 235 (0xeb): port 3 queue 0 egress limit control 1 register 251 (0xfb): port 4 queue 0 egress limit control 1 7 reserved ro 0 6 - 0 port queue 0 egress limit egress data rate limit for priority 0 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egre ss limit control registers. in four queues mode, it is lowest priority. in two queues mode, it is low priority. r/w 0000000 register 188 (0xbc): reserved register 204 (0xcc): port 1 queue 1 egress limit control 2 register 220 (0xdc): port 2 queue 1 egress limit control 2 register 236 (0xec): port 3 queue 1 egress limit control 2 register 252 (0xfc): port 4 queue 1 egress limit control 2 7 reserved ro 0 6 - 0 port queue 1 egress limit egress data rate limit for priority 1 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egre ss limit control registers. in four queues mode, it is low/high priority. in two queues mode, it is high priority. r/w 0000000 register 189 (0xbd): reserved register 205 (0xcd): port 1 queue 2 egress limit control 3 register 221 (0xdd): port 2 queue 2 egress limit control 3 register 237 (0xed): port 3 queue 2 egress limit control 3 register 253 (0xfd): port 4 queue 2 egress limit control 3 7 reserved ro 0 6 - 0 port queue 2 egress limit egress data rate limit for priority 2 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egre ss limit control registers. in four queues mode, it is high/low priority. r/w 0000000
micrel, inc. KSZ8864RMN september 2011 82 m9999-092011-1.4 address name description mode default register 190 (0xbe): reserved register 206 (0xce): port 1 queue 3 egress limit control 4 register 222 (0xde): port 2 queue 3 egress limit control 4 register 238 (0xee): port 3 queue 3 egress limit control 4 register 254 (0xfe): port 4 queue 3 egress limit control 4 and chip id 7 reserved and chip id =0 is for the register 206/222/238 =1 is KSZ8864RMN chip id for the register 254 ro 0 or 1 6 - 0 port queue 3 egress limit egress data rate limit for priority 3 frames egress traffic from this priority queue is shaped according to the data rate selected table. see the table follow the end of egre ss limit control registers. in four queues mode, it is highest priority. r/w 0000000 notes: 1. in the port priority 0-3 ingress rate limit mode, there is a need to set all related ingress/egress ports to two queues or f our queues mode. 2. in the port queue 0-3 egress rate limit mode, the highest priori ty get exact rate limit based on the rate select table, othe r priorities packets rate are based up on the ratio of the port register control 10/11/12/13 when use more than one egress queue per port. data rate selection table in 100bt rate for 100bt mode priority/queue 0-3 ingress/eg ress limit control register bit[6:0]= decimal 1 mbps <= rate <= 99 mbps rate(decimal integer 1-99) rate = 100 mbps 0 or 100 (decimal), ?0? is default value less than 1mbps see as below decimal 64 kbps 7?d101 128 kbps 7?d102 192 kbps 7?d103 256 kbps 7?d104 320 kbps 7?d105 384 kbps 7?d106 448 kbps 7?d107 512 kbps 7?d108 576 kbps 7?d109 640 kbps 7?d110 704 kbps 7?d111 768 kbps 7?d112 832 kbps 7?d113 896 kbps 7?d114 960 kbps 7?d115 table 11. 100bt rate sele ction for the rate limit
micrel, inc. KSZ8864RMN september 2011 83 m9999-092011-1.4 data rate selection table in 10bt rate for 10bt mode priority/queue 0-3 ingress/egre ss limit control register bit[6:0]= decimal 1 mbps <= rate <= 9 mbps rate(decimal integer 1-9) rate = 10 mbps 0 or 10 (decimal), ?0? is default value less than 1mbps see as below decimal 64 kbps 7?d101 128 kbps 7?d102 192 kbps 7?d103 256 kbps 7?d104 320 kbps 7?d105 384 kbps 7?d106 448 kbps 7?d107 512 kbps 7?d108 576 kbps 7?d109 640 kbps 7?d110 704 kbps 7?d111 768 kbps 7?d112 832 kbps 7?d113 896 kbps 7?d114 960 kbps 7?d115 table 12. 10bt rate selection for the rate limit address name description mode default register 191(0xbf): testing register 7 - 0 reserved n/a ro 0x80 register 207(0xcf): port3 control register 1 7 port 3 mac3 sw3-mii/rmii half duplex mode 1, enable sw3-mii/rmii in terface half duplex mode 0, enable sw3-mii/rmii in terface full duplex mode (default) r/w 0 6 port 3 mac3 sw3-mii/rmii flow control enable 1, enable full duplex flow control on sw3-mii/rmii interface 0, disable full duplex flow control on sw3-mii/rmii interface (default) r/w 0 5 port 3 mac3 sw3-mii/rmii speed setting 1, port 3 sw3-mii/rmii interface speed at 10bt. 0, port 3 sw3-mii/rmii in terface speed at 100bt (default) r/w 0 4 - 0 reserved n/a do not change. ro 0x15
micrel, inc. KSZ8864RMN september 2011 84 m9999-092011-1.4 address name description mode default register 223(0xdf): port3 control register 2 7 reserved reserved ro 0 6 select switch port 3 mac 3 sw3-mii interface mode 1, select switch port 3 mac3 interface as mac mode. 0, select switch port 3 mac3 interface as phy mode (default). r/w 0 5 - 0 reserved n/a do not change. ro 0x2c register 239(0xef): test register 3 7-0 reserved n/a do not change. ro 0x32 register 255(0xff): testing and port 4 control register 7 reserved n/a do not change. ro 0 6 invert phase of smtxc clock input for sw4-rmii 1 = invert the phase of sm4txc clock input in rmii mode, set this bit when connect sw4-rmii clock mode to sw4-rmii normal mode for two devices back to back connection at clock mode side of the device only. 0 = normal phase if sm4txc clock input r/w 0 5-0 reserved n/a do not change. ro 000000
micrel, inc. KSZ8864RMN september 2011 85 m9999-092011-1.4 static mac address table KSZ8864RMN has a static and a dynamic address table. when a da look-up is requested, both tables will be searched to make a packet forwarding decision. when an sa look-up is requested, only the dynamic table is searched for aging, migration, and learning purposes. the stat ic da look-up result will have precedence over the dynamic da look-up result. if there are da matches in both tables, the result fr om the static table will be used. the static table can only be accessed and cont rolled by an external spi master (usu ally a processor). the entries in the static table will not be aged out by KSZ8864RMN. an exter nal device does all addition, modification and deletion. note: register bit assignments are different for st atic mac table reads and static mac table write, as shown in the two tables below. address name description mode default format of static mac table for reads (32 entries) 63-57 fid filter vlan id, representing one of the 128 active vlans ro 0000000 56 use fid 1, use (fid+mac) to look-up in static table. 0, use mac only to look-up in static table. ro 0 55 reserved reserved. ro n/a 54 override 1, override spanning tree ?transmit enable = 0? or ?receive enable = 0* setting. this bit is used for spanning tree implementation. 0, no override. ro 0 53 valid 1, this entry is valid, the look-up result will be used. 0, this entry is not valid. ro 0 52-48 forwarding ports the 5 bits control the forward ports, example: 00001, reserved 00010, forward to port 1 ?.. 10000, forward to port 4 00110, forward to port 1 and port 2 11111, broadcasting (excluding the ingress port) ro 00000 47-0 mac address (da) 48 bit mac address. ro 0x0 format of static mac table for writes (32 entries) 62-56 fid filter vlan id, representing one of the 128 active vlans. w 0000000 55 use fid 1, use (fid+mac) to look-up in static table. 0, use mac only to look-up in static table. w 0 54 override 1, override spanning tree ?transmit enable = 0? or ?receive enable = 0? setting. this bit is used for spanning tree implementation. 0, no override. w 0 53 valid 1, this entry is valid, the look-up result will be used. 0, this entry is not valid. w 0
micrel, inc. KSZ8864RMN september 2011 86 m9999-092011-1.4 address name description mode default 52-48 forwarding ports the 5 bits control the forward ports, example: 00001, reserved 00010, forward to port 1 ?.. 10000, forward to port 4 00110, forward to port 1 and port 2 11111, broadcasting (excluding the ingress port) w 00000 47-0 mac address (da) 48-bit mac address. w 0x0 table 13. static mac address table
micrel, inc. KSZ8864RMN september 2011 87 m9999-092011-1.4 examples: (1) static address table read (read the 2nd entry) write to register 110 with 0x 10 (read static table selected) write to register 111 with 0x1 (trigger the read operation) then read register 113 (63-56) read register 114 (55-48) read register 115 (47-40) read register 116 (39-32) read register 117 (31-24) read register 118 (23-16) read register 119 (15-8) read register 120 (7-0) (2) static address table write (write the 8th entry) write to register 110 with 0x 10 (read static table selected) write register 113 (62-56) write register 114 (55-48) write register 115 (47-40) write register 116 (39-32) write register 117 (31-24) write register 118 (23-16) write register 119 (15-8) write register 120 (7-0) write to register 110 with 0x00 (write static table selected) write to register 111 with 0x7 (trigger the write operation)
micrel, inc. KSZ8864RMN september 2011 88 m9999-092011-1.4 vlan table the vlan table is used for vlan table look-up. if 802.1q vlan mode is enabled (register 5 bit 7 = 1), this table is used to retrieve vlan information that is associated with the ingress packet. the fields in cludes fid (filter id), valid and vlan membership need initializtion, the table is blank 4096 enties after reset, due to provide 4k spacing for the vlan table, there is no vid filed bits, vid is used as entries address index to input up to 40 96 entries with bits [12:0] information. address name description mode initial value suggestion format of static vlan table (support max 4096 vlan id entries and 128 active vlans) 12 valid 1, the entry is valid. 0, entry is invalid. r/w 0 11-7 membership specify which ports are members of the vlan. if a da look-up fails (no match in both static and dynamic tables), the packet associated with this vlan will be forwarded to ports sp ecified in this field. e.g., 11010 means ports 4, 3, and 1 are in this vlan. last bit7 is reserved r/w 11111 6-0 fid filter id. KSZ8864RMN supports 128 active vlans represented by these seven bit fields. fid is the mapped id. if 802.1q vlan is enabled, the look-up will be based on fid+da and fid+sa. r/w 0 table 14. vlan table if 802.1q vlan mode is enabled, KSZ8864RMN assigns a vid to every ingress packet when the packet is untagged or tagged with a null vid, the packet is assigned with the default port vid of th e ingress port. if the packet is tagged with non-null vid, the vid in the tag is used. the look- up process starts from the vl an table look-up based on vid number. if the entry is not valid in vlan table, the pack et is dropped and no address learning occurs. if the entry is valid, the fid is retrieved. the fid+da and fid+sa look ups in mac tables are perf ormed. the fid+da look-up determines the forwarding ports. if fid+da fails for look-up in mac table, the packet is broadcast to all the members or specified members (excluding the ingress port) based on the vlan table. if fid+sa fails, the fid+sa is learned. if want to communicate between diffe rent active vlans, set same fid, otherwise set different fid. the vlan table configuration is organized as 1024 vlan se ts, each vlan set consists of 4 vlan entries, to support up to 4096 vlan entries. each vlan set has 52 bits and should be read or written at the same time specified by the indirect address. the vlan entries in the vlan set is mapped to indirect data registers as follow: entry0[12:0] maps to the vlan set bits[ 12-0] {register119[4:0 ], register120[7:0]} entry1[12:0] maps to the vlan set bits[25-13]{reg ister117[1:0], register118[7: 0], register119[7:5]} entry2[12:0] maps to the vlan set bits [38-26]{register116[6:0], register117[7:2]} entry3[12:0] maps to the vlan set bits[51-39]{r egister114[3:0], register115[7:0], register116[7]} in order to read one vlan entry, the vlan set is read first and the specific vlan entry information can be extracted. to update any vlan entry, the vlan set is read first then only the desired vlan entry is updated and the whole vlan set is written back. due to fid in vlan table is 7-bit, so the vlan table supports unique 128 flow vlan groups. each vlan set address is 10 bits long (maximum is 1024) in the indirect addres s register 110 and 111, the bit [9-8] of vlan set address is at bit [1-0] of register 11 0, and the bit [7-0] of vlan set address is at bit [7-0] of register 111. each write and read can ac cess to four consecutive vlan entries.
micrel, inc. KSZ8864RMN september 2011 89 m9999-092011-1.4 examples: (1) vlan table read (read the vid=2 entry) write the indirect control and address registers first write to register 110 (0x6e) with 0x14 (read vlan table selected) write to register 111 (0x6f) with 0x0 (trigger the read operation for vid=0, 1, 2, 3 entries) then read the indirect data register s bits [38-26] for vid=2 entry read register 116 (0x74), (register116[6:0] are bits 12-6 of vlan vid=2 entry) read register 117 (0x75), (register117[7: 2] are bits 5-0 of vlan vid=2 entry) (2) vlan table write (write the vid=10 entry) read the vlan set that contains vid=8, 9, 10, 11. write to register 110 (0x6e) with 0x14 (read vlan table selected) write to register 111 (0x6f) with 0x02 (trigger t he read operation and vid=8, 9, 10, 11 indirect address) read the vlan set first by the indirect data registers 114, 115, 116, 117, 118, 119, 120. modify the indirect data r egisters bits [38-26] by t he register 116 bit [6-0] and register 117 bit [7-2] as follows: write to register 116 (0x74), (register116 [6 :0] are bits 12-6 of vl an vid=10 entry) write to register 117 (0x75), (register117 [7:2] are bits 5-0 of vlan vid=10 entry) then write the indirect control and address registers write to register 110 (0x6e) with 0x04 (write vlan table selected) write to register 111 (0x6f) with 0x02 (trigger the write operation and vid=8, 9, 10, 11 indirect address) the table of the follow shows the relationship of the indirect address/data registers and vlan id. indirect address high/low bit[9-0] for vlan sets indirect data registers bits for each vlan entry vid numbers vid bit[12-2] in vlan tag vid bit[1-0] in vlan tag 0 bits[12-0] 0 0 0 0 bits[25-13] 1 0 1 0 bits[38-26] 2 0 2 0 bits[51-39] 3 0 3 1 bits[12-0] 4 1 0 1 bits[25-13] 5 1 1 1 bits[38-26] 6 1 2 1 bits[51-39] 7 1 3 2 bits[12-0] 8 2 0 2 bits[25-13] 9 2 1 2 bits[38-26] 10 2 2 2 bits[51-39] 11 2 3 : : : : : : : : : : : : : : : 1023 bits[12-0] 4092 1023 0 1023 bits[25-13] 4093 1023 1 1023 bits[38-26] 4094 1023 2 1023 bits[51-39] 4095 1023 3 table 15. vlan id and indirect registers
micrel, inc. KSZ8864RMN september 2011 90 m9999-092011-1.4 dynamic mac address table this table is read only. the contents are maintained by the KSZ8864RMN only. address name description mode default format of dynamic mac address table (1k entries) 71 mac empty 1, there is no valid entry in the table. 0, there are valid entries in the table. ro 1 70-61 no of valid entries indicates how many valid entries in the table. 0x3ff means 1k entries 0x1 and bit 71 = 0: means 2 entries 0x0 and bit 71 = 0: means 1 entry 0x0 and bit 71 = 1: means 0 entry ro 0 60-59 time stamp 2-bit counters for internal aging ro 58-56 source port the source port where fid+mac is learned. 000 port 1 001 port 2 010 port 3 011 port 4 100 port 5 ro 0x0 55 data ready 1, the entry is not ready, retr y until this bit is set to 0. 0, the entry is ready. ro 54-48 fid filter id. ro 0x0 47-0 mac address 48-bit mac address. ro 0x0 table 16. dynamic mac address table examples: (1) dynamic mac address table read (read the 1 st entry), and retrieve the mac table size write to register 110 with 0x18 (read dynamic table selected) write to register 111 with 0x0 (tri gger the read operation) and then read register 112 (71-64) read register 113 (63-56); // the above two registers show # of entries read register 114 (55-48) // if bit 55 is 1, restart (reread) from this register read register 115 (47-40) read register 116 (39-32) read register 117 (31-24) read register 118 (23-16) read register 119 (15-8) read register 120 (7-0)
micrel, inc. KSZ8864RMN september 2011 91 m9999-092011-1.4 (2) dynamic mac address table read (read the 257 th entry), without retrieving # of entries information write to register 110 with 0x19 (read dynamic table selected) write to register 111 with 0x1 (tri gger the read operation) and then read register 112 (71-64) read register 113 (63-56) read register 114 (55-48) // if bit 55 is 1, restart (reread) from this register read register 115 (47-40) read register 116 (39-32) read register 117 (31-24) read register 118 (23-16) read register 119 (15-8) read register 120 (7-0)
micrel, inc. KSZ8864RMN september 2011 92 m9999-092011-1.4 mib (management information base) counters the mib counters are provided on per port basis. these coun ters are read using indirect memory access as below: for port 1 offset counter name description 0x20 rxloprioritybyte rx lo-priority (def ault) octet count including bad packets. 0x21 rxhiprioritybyte rx hi-prior ity octet count including bad packets. 0x22 rxundersizepkt rx undersize packets w/good crc. 0x23 rxfragments rx fragment packets w/bad cr c, symbol errors or alignment errors. 0x24 rxoversize rx oversize packets w/good crc (max: 1536 or 1522 bytes). 0x25 rxjabbers rx packets longer than 1522b w/either cr c errors, alignment errors, or symbol errors (depends on max packet size setting) or rx packets longer than 1916b only. 0x26 rxsymbolerror rx packets w/ invalid data symbol and legal preamble, packet size. 0x27 rxcrcerror rx packets within (64,1522) bytes w/an integral number of bytes and a bad crc (upper limit depends up on max packet size setting). 0x28 rxalignmenterror rx packets within (64,1522) byte s w/a non-integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0x29 rxcontrol8808pkts the number of mac control fram es received by a port with 88-08h in ethertype field. 0x2a rxpausepkts the number of pause frames received by a port. pause frame is qualified with ethertype (88- 08h), da, control opcode (00-01), data length (64b min), and a valid crc. 0x2b rxbroadcast rx good broadcast packets (not including errored broadcast packets or valid multicast packets). 0x2c rxmulticast rx good multicast packets (not includi ng mac control frames, errored multicast packets or valid broadcast packets). 0x2d rxunicast rx good unicast packets. 0x2e rx64octets total rx packets (bad packets included) that were 64 octets in length. 0x2f rx65to127octets total rx packets (bad packets in cluded) that are between 65 and 127 octets in length. 0x30 rx128to255octets total rx packets (bad packets in cluded) that are between 128 and 255 octets in length. 0x31 rx256to511octets total rx packets (bad packets in cluded) that are between 256 and 511 octets in length. 0x32 rx512to1023octets total rx packets (bad packets in cluded) that are between 512 and 1023 octets in length. 0x33 rx1024to1522octets total rx packets (bad packets in cluded) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting). 0x34 txloprioritybyte tx lo-priority good octet count, including pause packets. 0x35 txhiprioritybyte tx hi-priority good octet count, including pause packets. 0x36 txlatecollision the number of times a collision is detected later than 512 bit-times into the tx of a packet. 0x37 txpausepkts the number of pause frames transmitted by a port. 0x38 txbroadcastpkts tx good broadcast packets (not in cluding errored broadcast or valid multicast packets). 0x39 txmulticastpkts tx good multicast packets (not includi ng errored multicast packets or valid broadcast packets). 0x3a txunicastpkts tx good unicast packets. 0x3b txdeferred tx packets by a port for which t he 1st tx attempt is delayed due to the busy medium. 0x3c txtotalcollision tx tota l collision, half-duplex only. 0x3d txexcessivecollision a count of frames for which tx fails due to excessive collisions. 0x3e txsinglecollision successfully tx frames on a por t for which tx is inhibited by exactly one collision. 0x3f txmultiplecollision successfully tx frames on a por t for which tx is inhibited by more than one collision. table 17. port-1 mib counter indirect memory offsets
micrel, inc. KSZ8864RMN september 2011 93 m9999-092011-1.4 for port 2, the base is 0x40, same offset definition (0x40-0x5f) for port 3, the base is 0x60, same offset definition (0x60-0x7f) for port 4, the base is 0x80, same offset definition (0x80-0x9f) address name description mode default format of per port mib counters (16 entries) 31 overflow 1, counter overflow. 0, no counter overflow. ro 0 30 count valid 1, counter value is valid. 0, counter value is not valid. ro 0 29-0 counter values counter value. ro 0 table 18. format of ?per port? mib counter offset counter name description 0x100 reserved reserved. 0x101 port1 tx drop packets tx packets dropped due to lack of resources. 0x102 port2 tx drop packets tx packets dropped due to lack of resources. 0x103 port3 tx drop packets tx packets dropped due to lack of resources. 0x104 port4 tx drop packets tx packets dropped due to lack of resources. 0x105 reserved reserved 0x106 port1 rx drop packets rx packe ts dropped due to lack of resources. 0x107 port2 rx drop packets rx packe ts dropped due to lack of resources. 0x108 port3 rx drop packets rx packe ts dropped due to lack of resources. 0x109 port4 rx drop packets rx packe ts dropped due to lack of resources. table 19. all port dropped packet mib counters address name description mode default format of all port dropped packet mib counters 30-16 reserved reserved. n/a n/a 15-0 counter values counter value. ro 0 table 20. format of ?all dropped packet? mib counter note: all port dropped packet mib counters do not indi cate overflow or validity; therefore t he application must keep track of overflo w and valid conditions. the KSZ8864RMN provides a total of 34 mib counter per po rt. these counter are used to monitor the port detail activity for network management and maintenance. these mib counters are read using indirect memory access as follows examples.
micrel, inc. KSZ8864RMN september 2011 94 m9999-092011-1.4 programming examples: (1) mib counter read (read port 1 rx64octets counter) write to register 110 with 0x1c (read mib counters selected) write to register 111 with 0x2e (trigger the read operation) then read register 117 (counter value 31-24) // if bit 31 = 1, there was a counter overflow // if bit 30 = 0, restart (re read) from this register read register 118 (counter value 23-16) read register 119 (counter value 15-8) read register 120 (counter value 7-0) (2) mib counter read (read port 2 rx64octets counter) write to register 110 with 0x1c (read mib counter selected) write to register 111 with 0x4e (trigger the read operation) then read register 117 (counter value 31-24) //if bit 31 = 1, there was a counter overflow //if bit 30 = 0, restart (reread) from this register read register 118 (counter value 23-16) read register 119 (counter value 15-8) read register 120 (counter value 7-0) (3) mib counter read (read port 1 tx drop packets) write to register 110 with 0x1d write to register 111 with 0x01 then read register 119 (counter value 15-8) read register 120 (counter value 7-0) note: to read out all the counters, the best performance over the spi bus is (160+3) 8 80 = 104us, where there are 160 registers, three overhead, eight clocks per access, at 12.5mhz. in the heaviest condition, the byte counter w ill overflow in two minutes. it is recommende d that the software read all the counters at least every 30 seconds. the per port mib counters are designed as ?read clear.? a per port mib counter will be cleared after it is accessed. all port dropped pa cket mib counters are not cleared after they are accessed. the application needs to ke ep track of overflow and valid conditions on these counters.
micrel, inc. KSZ8864RMN september 2011 95 m9999-092011-1.4 miim registers all the registers defined in this section can be also accessed via the spi interface. note: different mapping mechanisms used for miim and spi. the ?phyad? defined in KSZ8864RMN is assigned as ?0x2? for port 1, ?0x3? for port 2. the ?phyad? of 0x1, 0x4 and 0x5 are reserved fo r this device, an external phy can use other phy address (phyad) from 0x6. the ?regad? supported are 0x0-0x5 (0h-5h), 0x1d (1dh) and 0x1f (1fh). address name description mode default register 0h: mii control 15 soft reset 1, phy soft reset. 0, normal operation. r/w (sc) 0 14 loop back 1 = perform mac loopback, loop back path as follows: assume the loop-back is at port 1 mac, port 2 is the monitor port. port 1 mac loopback (port 1 reg. 0, bit 14 = ?1?) start: rxp2/rxm2 (port 2). can also start from port 3, 4, 5 loopback: mac/phy interface of port 1?s mac end: txp2/txm2 (port 2). can also end at port 3, 4, 5 respectively setting address ox3,4,5 reg. 0, bit 14 = ?1? will perform mac loopback on port 3, 4, 5 respectively. 0 = normal operation. r/w 0 13 force 100 1, 100mbps. 0, 10mbps. r/w 1 12 an enable 1, auto-negotiation enabled. 0, auto-negotiation disabled. r/w 1 11 power down 1, power down. 0, normal operation. r/w 0 10 phy isolate 1, electrical ph y isolation of phy from tx+/tx-. 0, normal operation. r/w 0 9 restart an 1, restart auto-negotiation. 0, normal operation. r/w 0 8 force full duplex 1, full duplex. 0, half duplex. r/w 0 7 collision test not supported. ro 0 6 reserved ro 0 5 hp_mdix 1 = hp auto mdi/mdi-x mode 0 = micrel auto mdi/mdi-x mode r/w 1 4 force mdi 1, force mdi. 0, normal operation. r/w 0 3 disable auto mdi/mdi-x 1, disable auto mdi/mdi-x. 0, normal operation. r/w 0
micrel, inc. KSZ8864RMN september 2011 96 m9999-092011-1.4 address name description mode default 2 disable far end fault 1, disable far end fault detection. 0, normal operation. r/w 0 1 disable transmit 1, disable transmit. 0, normal operation. r/w 0 0 disable led 1, disable led. 0, normal operation. r/w 0 register 1h: mii status 15 t4 capable 0, not 100 baset4 capable. ro 0 14 100 full capable 1, 100base-tx full-duplex capable. 0, not capable of 100base-tx full-duplex. ro 1 13 100 half capable 1, 100base-tx half-duplex capable. 0, not 100base-tx half-duplex capable. ro 1 12 10 full capable 1, 10 base-t full-duplex capable. 0, not 10base-t full-duplex capable. ro 1 11 10 half capable 1, 10base-t half-duplex capable. 0, 10base-t half-duplex capable. ro 1 10-7 reserved ro 0 6 preamble suppressed not supported. ro 0 5 an complete 1, au to-negotiation complete. 0, auto-negotiation not completed. ro 0 4 far end fault 1, far end fault detected. 0, no far end fault detected. ro 0 3 an capable 1, auto-negotiation capable. 0, not auto-negotiation capable. ro 1 2 link status 1, link is up. 0, link is down. ro 0 1 jabber test not supported. ro 0 0 extended capable 0, not extended register capable. ro 0 register 2h: phyid high 15-0 phyid high high order phyid bits. ro 0x0022 register 3h: phyid low 15-0 phyid low low order phyid bits. ro 0x1450 register 4h: advertisement ability 15 next page not supported. ro 0 14 reserved ro 0 13 remote fault not supported. ro 0
micrel, inc. KSZ8864RMN september 2011 97 m9999-092011-1.4 address name description mode default 12-11 reserved ro 0 10 pause 1, advertise pause ability. 0, do not advertise pause ability. r/w 1 9 reserved r/w 0 8 adv 100 full 1, advertise 100 full-duplex ability. 0, do not advertise 100 full-duplex ability. r/w 1 7 adv 100 half 1, advertise 100 half-duplex ability. 0, do not advertise 100 half-duplex ability. r/w 1 6 adv 10 full 1, advertise 10 full-duplex ability. 0, do not advertise 10 full-duplex ability. r/w 1 5 adv 10 half 1, advertise 10 half-duplex ability. 0, do not advertise 10 half-duplex ability. r/w 1 4-0 selector field 802.3 ro 00001 register 5h: link partner ability 15 next page not supported. ro 0 14 lp ack not supported. ro 0 13 remote fault not supported. ro 0 12-11 reserved ro 0 10 pause 1, link partner flow control capable. 0, link partner not flow control capable. ro 0 9 reserved ro 0 8 adv 100 full 1, link partner 100bt full-duplex capable. 0, link partner not 100bt full-duplex capable. ro 0 7 adv 100 half 1, link partner 100bt half-duplex capable. 0, link partner not 100bt half-duplex capable. ro 0 6 adv 10 full 1, link partner 10bt full-duplex capable. 0, link partner not 10bt full-duplex capable. ro 0 5 adv 10 half 1, link partner 10bt half-duplex capable. 0, link partner not 10bt half-duplex capable. ro 0 4-0 reserved ro 00001 register 1dh: reserved 15 reserved ro 0 14-13 reserved ro 00 12 reserved ro 0 11-9 reserved ro 0 8-0 reserved ro 000000000
micrel, inc. KSZ8864RMN september 2011 98 m9999-092011-1.4 address name description mode default register 1fh: phy special control/status 15-11 reserved ro 0000000000 10-8 port operation mode indication indicate the current stat e of port operation mode: [000] = reserved. [001] = still in auto-negotiation. [010] = 10base-t half duplex. [011] = 100base-tx half duplex. [100] = reserved. [101] = 10base-t full duplex. [110] = 100base-tx full duplex. [111] = phy/mii isolate. ro 000 7-6 reserved n/a, do not change. r/w xx 5 polrvs 1 = polarity is reversed. 0 = polarity is not reversed. ro 0 4 mdi-x status 1 = mdi-x 0 = mdi ro 0 3 force_lnk 1 = force link pass. 0 = normal operation. r/w 0 2 pwrsave 1 = enable power save. 0 = disable power save. r/w 0 1 remote loopback 1 = perform remote loopback, loop back path as follows: port 1 (phy id address 0x1 reg. 1f, bit 1 = ?1?) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 1?s phy end: txp1/txm1 (port 1) setting phy id address 0x2,3,4,5 reg. 1f, bit 1 = ?1? will perform remote loopback on port 2, 3, 4, 5. 0 = normal operation. r/w 0 0 reserved ro 0
micrel, inc. KSZ8864RMN september 2011 99 m9999-092011-1.4 absolute maximum ratings (1) supply voltage (v ddar , v ddc ) ..................................?0.5v to +2.4v (v ddat , v ddio ) .................................?0.5v to +4.0v input volt age ........................................?0.5v to +4.0v output voltage .....................................?0.5v to +4.0v lead temperature (solder ing, 10 sec.) ..............260c storage temperature (t s ) ................ ?55c to +150c hbm esd ra ting................................................... 2kv operating ratings (2) supply voltage (v ddar , v ddc )..............................+1.15v to +1.25v (v ddat )........................................+3.15v to +3.45v (v ddio )3.15 to 3.45v or 2.4 to 2.6v or 1.71 to 1.89v ambient temperature (t a ) commercial..................................... ?0c to +70c industrial ....................................... ?40c to +85c max junction temperature (t j ) ......................... 125c package thermal resistance (3) thermal resistance ( ja ) .................... 31.96c/w thermal resistance ( jc )..................... 13.54c/w electrical characteristics (4, 5) v in = 1.2v/3.3v (typ.); t a = 25c symbol parameter condition min typ max units 100base-tx operation?all ports 100% utilization i dx 100base-tx (transmitter) 3.3v analog v ddat 54 ma i dda 100base-tx 1.2v analog v ddar 23 ma i ddc 100base-tx 1.2v digital v ddc 41 ma i ddio 100base-tx (digital io) 3.3v digital v ddio 12 ma 10base-t operation ?all ports 100% utilization i dx 10base-t (transmitter) 3.3v analog v ddat 54 ma i dda 10base-t 1.2v analog v ddar 14 ma i ddc 10base-t 1.2v digital v ddc 43 ma i ddio 10base-t (digital io) 3.3v digital v ddio 12 ma auto-negotiation mode i dx 10base-t (transmitter) 3.3v analog v ddat 32 ma i dda 10base-t 1.2v analog v ddar 24 ma i edm 10base-t 1.2v digital v ddc 59 ma i ddio 10base-t (digital io) 3.3v digital v ddio 12 ma power management mode i psm1 power saving mode 3.3v v ddat + v ddio 30 ma i psm2 power saving mode 1.2v v ddar + vddc 74 ma i spdm1 soft power down mode 3.3v v ddat + v ddio 2 ma i spdm2 soft power down mode 1.2v v ddar + vddc 0.55 ma i edm1 energy detect mode 3.3v v ddat + v ddio 14 ma i edm2 energy detect mode 1.2v v ddar + vddc 47 ma
micrel, inc. KSZ8864RMN september 2011 100 m9999-092011-1.4 symbol parameter condition min typ max units ttl inputs v ih input high voltage (vddio=3.3/2.5/1.8v) 2.0/2.0 /1.3 v v il input low voltage (vddio=3.3/2.5/1.8v) 0.8/0. 6/0.3 v i in input current (excluding pull-up/pull-down) v in = gnd ~ v ddio ?10 10 a ttl outputs v oh output high voltage (vddio=3.3/2.5/1.8v) i oh = ?8ma 2.4/1.9 /1.5 v v ol output low voltage (vddio=3.3/2.5/1.8v) i ol = 8ma 0.4/0. 4/0.2 v i oz output tri-state leakage v in = gnd ~ v ddio 10 a 100base-tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 ? termination on the differential output 0.95 1.05 v v imb output voltage imbalance 100 ? termination on the differential output 2 % rise/fall time 3 5 ns t r t t rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.5 ns overshoot 5 % output jitters peak-to-peak 0 0.75 1.4 ns 10base-t receive v sq squelch threshold 5mhz square wave 300 400 585 mv 10base-t transmit (measured differentially after 1:1 transformer) v ddat = 3.3v v p peak differential output voltage 100 ? termination on the differential output 2.2 2.5 2.8 v output jitters peak-to-peak 1.4 3.5 ns rise/fall times 28 30 ns notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to functi on outside its operating rating. unused inputs must always be tied to an appropriate l ogic voltage level (ground or v dd ). 3. no heat spreader in package. the thermal junction to ambient ( ja ) and the thermal junction to case ( jc ) are under air velocity 0m/s. 4. specification for packaged product only. there is no an additi onal transformer consumption due to use on chip termination te chnology with internal biasing for 10bese-t and 100base-tx. 5. measurements were taken with operating ratings.
micrel, inc. KSZ8864RMN september 2011 101 m9999-092011-1.4 timing diagrams eeprom timing figure 13. eeprom interface input receive timing diagram figure 14. eeprom interface output transmit timing diagram symbol parameter min typ max units t cyc1 clock cycle 16384 ns t s1 set-up time 20 ns t h1 hold time 20 ns t ov1 output valid 4096 4112 4128 ns table 21. eeprom timing parameters
micrel, inc. KSZ8864RMN september 2011 102 m9999-092011-1.4 mii timing figure 15. mac mode mii timing ? data received from mii figure 16. mac mode mii timing ? data transmitted from mii 10base-t/100base-tx symbol parameter min. typ. max. units t cyc3 clock cycle 400/40 ns t s3 set-up time 10 ns t h3 hold time 5 ns t ov3 output valid 3 9 25 ns table 22. mac mode mii timing parameters
micrel, inc. KSZ8864RMN september 2011 103 m9999-092011-1.4 figure 17. phy mode mii timing ? data received from mii figure 18. phy mode mii timing ? data transmitted from mii 10baset/100baset symbol parameter min typ max unit s t cyc4 clock cycle 400/40 ns t s4 set-up time 10 ns t h4 hold time 0 ns t ov4 output valid 10 20 25 ns table 23. phy mode mii timing parameters
micrel, inc. KSZ8864RMN september 2011 104 m9999-092011-1.4 rmii timing refclk tcyc tx_en txd[1:0] t1 t2 transmit timing figure 19. rmii timing ? data received from rmii refclk tcyc tod crsdv rxd[1:0] receive timing figure 20. rmii timing ? data transmitted to rmii timing parameter description min typ max unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 3 14 ns table 24. rmii timing parameters
micrel, inc. KSZ8864RMN september 2011 105 m9999-092011-1.4 spi timing spiq spic spid spis_n high impedance msb tchsl tslch tdvch tchdx tdldh tdhdl lsb tclch tchcl tshch tchsh tshsl figure 21. spi input timing symbol parameter min typ max units f c clock frequency 25 mhz t chsl spis_n inactive hold time 10 ns t slch spis_n active set-up time 10 ns t chsh spis_n active hold time 10 ns t shch spis_n inactive set-up time 10 ns t shsl spis_n deselect time 200 ns t dvch data input set-up time 5 ns t chdx data input hold time 5 ns t clch clock rise time 1 s t chcl clock fall time 1 s t dldh data input rise time 1 s t dhdl data input fall time 1 s table 25. spi input timing parameters
micrel, inc. KSZ8864RMN september 2011 106 m9999-092011-1.4 figure 22. spi output timing symbol parameter min typ max units f c clock frequency 25 mhz t clqx spiq hold time 0 0 ns t clqv clock low to spiq valid 15 ns t ch clock high time 18 ns t cl clock low time 18 ns t qlqh spiq rise time 50 ns t qhql spiq fall time 50 ns t shqz spiq disable time 15 ns table 26. spi output timing parameters
micrel, inc. KSZ8864RMN september 2011 107 m9999-092011-1.4 auto-negotiation timing figure 23: auto-negotiation timing symbol parameter min typ max units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per burst 17 33 table 27. auto-negotiation timing parameters
micrel, inc. KSZ8864RMN september 2011 108 m9999-092011-1.4 mdc/mdio timing figure 24. mdc/mdio timing timing parameter description min typ max unit t p mdc period 400 ns t 1md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 4 ns t md3 mdio (phy output) delay from rising edge of mdc 222 ns table 28. mdc/mdio typical timing parameters
micrel, inc. KSZ8864RMN september 2011 109 m9999-092011-1.4 reset timing figure 25. reset timing symbol parameter min typ max units t sr stable supply voltages to reset high 10 ms t cs configuration set-up time 50 ns t ch configuration hold time 50 ns t rc reset to strap-in pin output 50 ns tvr 3.3v rise time 100 us table 29. reset timing parameters
micrel, inc. KSZ8864RMN september 2011 110 m9999-092011-1.4 reset circuit diagram micrel recommends the following discrete reset circuit, as shown in figure 26, when powering up the ks8895mq device. for the application where the rese t circuit signal comes from another device (e.g., cpu, fpga, etc), micrel recommends the reset circuit, as shown in figure 27. figure 26. recommended reset circuit figure 27. recommended circuit for interfacing with cpu/fpga reset in the reset circuit, r, c, and d1 provide the necessary ramp rise time to reset the micrel device. the d2 is for isolation between micrel device and cpu/fpga. the reset out rst_out_n from cpu/fpga can provides the warm reset after power-up.
micrel, inc. KSZ8864RMN september 2011 111 m9999-092011-1.4 selection of isolation transformer (1) one simple 1:1 isolation transformer is needed at the line in terface. an isolation transformer with integrated common- mode choke is recommended for exceeding fcc requirements at line side. request to separate the center taps of rx/tx at chip side. table 30 gives re commended transformer characteristics. characteristics name value test condition turns ratio 1 ct : 1 ct open-circuit inductance (minimum) 350h 100mv, 100khz, 8ma leakage inductance (maximum) 0.4h 1mhz (min.) inter-winding capacitance (maximum) 12pf d.c. resistance (maximum) 0.9 ? insertion loss (maximum) 1.0db 0mhz to 65mhz hipot (minimum) 1500vrms table 30. transformer selection criteria notes: 1. the ieee 802.3u standard for 100base-tx assumes a transformer lo ss of 0.5db. for the transmit line transformer, insertion lo ss of up to 1.3db can be compensated by increasing the line drive current by means of reducing the iset resistor value. 2. the center taps of rx and tx should be isolated for the low power consumption. the following transformer vendors provide com patible magnetic parts for micrel?s device: single port integrated single port vendor part auto mdix number of ports vendor part auto mdix number of ports tdk tla-6t718a yes 1 pulse h1102 yes 1 lankom lf-h41s yes 1 bel fuse s558-5999-u7 yes 1 transpower hb726 yes 1 ycl pt163020 yes 1 delta lf8505 yes 1 datatronic nt79075 yes 1 table 31. qualified magnetic vendors selection of reference crystal chacteristics value units frequency 25.00000 mhz frequency tolerance (maximum) ? = ? 50 ppm load capacitance (maximum) 27 pf series resistance (max esr) 40 ? table 32. typical reference crystal characteristics
micrel, inc. KSZ8864RMN september 2011 112 m9999-092011-1.4 package information 64-pin (8mm x 8mm) qfn package micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com micrel makes no representations or warranties with respect to t he accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for it s use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or other wise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support applianc es, devices or systems is a pu rchaser?s own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2011 micrel, incorporated.


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